AM3715: DSS PLL spread spectrum clocking

Hi,

Have you followed the guidelines from section 13.4.11 of the AM37x TRM Rev. R ?

Hi Biser,

Yes, I followed the section 13.4.11 of AM37x TRM Rev.R to calculate the parameters of CONTROL_DSS_DPLL_SPREADING_FREQ.
But I am not sure it’s a reasonable spreading frequency.
Do you have any advice?

Best Regards,
Mason

At what frequencies do you observe peaks? How much dB are they above limit?

Refer to Section 13.4.11.4.1 SSC Configuration
1. Fref = Finp / (N+1) = 26MHz / (12+1) = 2MHz
2. Must Fm < Fref / 70
2MHz / 70 = 28KHz
So I using 20K for spreading frequency.
PPR = 10 * log(0.1 * 172 / 0.02) = 29.3 dB
3. ModFreqDivider = Fref / (4*fm) = 2 / (4 * 0.02) = 2 / 0.08 = 25 = 25 * 2^0
so MANT is 25 and EXP is 0
4. DeltaM = M * percentage of fc / ModFreqDivider = 432 * 0.1 / 25 = 1.728
so DELTA_M_INT is 1.
DELTA_M_FRACT = 0.728 * 2^18 = 190840

Best Regards,

Mason

Can you please answer my questions from the previous post?

At what frequencies do you observe peaks? harmonic frequencies of 24.68MHz
How much dB are they above limit? 10 dB

Best Regards,
Mason

Thanks. We are looking into this. Feedback will be posted here.

Hi Biser,
Thank you very much!

Best Regards,
Mason

Mason, what does the DSS_SPREADING_ENABLE_STATUS bit indicate?

Regards,
James

Hi Mason, sorry i didn't see your registers earlier in the post. It looks like the status bit is set, so the SSC should be properly enabled. I'm not sure what could be going wrong, i checked your calculations and they look correct.

One issue I see is that you are declaring a 10% frequency deviation, which would result in a possible DSS1_ALWON_FCLK of 155MHz-190MHz. The max functional clock of the DSS is 173MHz, so you would be violating the its spec when enabling SSC. You must keep the functional clock <173MHz to the DSS.

You can try a couple of things to avoid this:
- enable Q_DSS_SPREADING_SIDE bit. The will enable low frequency spreading only, which means the spreading will be twice as much on the low side, and 0 on the high side. This would equate to DSS1_ALWON_FCLK of 138.24-172.8MHz
-reduce the DSS1_ALWON_FCLK so that the high side of the spread frequency does not move greater than 172.8MHz

Also, you may want to try with a smaller frequency deviation, for example, maybe 1% as in the example in the TRM.

With 1% deviation, Fm=17.28KHz, you get a PPR of 20dB and

MOD_FREQ_MAN = 0x1D
MOD_FREQ_EXP = 0

DeltaM = 0.148965517
DELTA_M_INT = 0
DELTA_M_FRAC = 0x988B

Regards,
james

Hi James,

Thank you very much for your help.

I've tried your suggestion - a smaller frequency deviation 1%.

But I got nothing different.

Here's the photo of analyzer.

It's the same as the wave without SSC enabled.

 

---

Also, I tried to reduce the DSS1_ALWON_FCLK.
The following is how I calculate.

 

Set 5% deviation,

For DPLL4, M=432, N=12, M5=7

DSS1_ALWON_FCLK = (Fin * M) / (N+1) / M5 = (26*432) / (12+1) / 7 = 123.4 MHz

Fout = DSS1_ALWON_FCLK = 123.4 MHz

Fref = Finp / (N+1) = 26 / (12+1) = 2 MHz

fc = 123.4 MHz

fm = 12.34 KHz = 0.01234 MHz

PPR = 10 * log (0.05 * 123.4 / 0.01234) = 26.99 dB

Check: Deviation = (fm / fc) * 10 ^ (PPR/10) = 0.05 = 5%

 

ModFreqDivider = Fref / (4 * fm ) = 2 * (4 * 0.01234) = 41

so

MOD_FREQ_MAN = 41
MOD_FREQ_EXP = 0

DeltaM = M * deviation / ModFreqDivider = 432 * 0.05 / 41 = 0.526829

so

DELTA_M_INT = 0
DELTA_M_FRAC = 0.526829 * 2^18 = 138105

 

Using deduced DSS1_ALWON_FCLK also got the same result.

 

The pixel clock is 123.4MHz / 5 = 24.68

814.633 MHz seems near the 33 times of 24.68 MHz

 

Do you have any idea about why SSC doesn’t work?

I have a thread to monitor the register CONTROL_DSS_DPLL_SPREADING.

And it is always 0x00000090.

So I think I have truned on the SSC.

 

Is there any sequence between turn on DSS pixel clock and SSC?

 

Thanks!

 

Best Regards,

Mason

Mason, in the above changes where you reduced the pixel clock frequency, you need to change the M4 divider, not M5.

I don't have a good explanation why you are not seeing any change at all. You should be locking the PLL first, then configuring the SSC.

Can you try significantly reducing the M multiplier from 432 to something smaller (something close to the example) and then also susequently reducing the N divider.

Also, what is the value you have for PRM_CLKSRC_CTRL.DPLL4_CLKINP_DIV?

Regards,
James

Hi James, thanks again!

You are right, the pixel clock divider is M4 not M5. I just typed wrong here. My source code is using M4.

The value of PRM_CLKSRC_CTRL.DPLL4_CLKINP_DIV is 0.

I will reduce the M and N multiplier and try again.

Thanks!

Hi James,
I’ve tried reducing the M and N for DPLL4.
M=100, N=2, M4=7
Thus,
Fout = (26x100) / (2+1) / 7 = 123.8 MHz
Fref = 26 / (2+1) = 8.6 MHz
Fm = 12.38 KHz
deviation 5%
PPR = 10 x log (0.05 x 123.8 / 0.01238) = 26.99 dB
ModFreqDivider = 8.6 / (4 * fm) = 174 = 87 * 2 ^ 1
MANT = 87
EXP = 1
DeltaM = M * 0.05 / ModFreqDivider = 100 * 0.05 / 87 = 0.0287356
DELTA_M_INT = 0
DELTA_M_FRACT = 0.0287356 * 2^18 = 7533

But it still can’t work.


Also I tried using:
M=28, N=2, M4=2
But this setting makes the UART3 fail.
(Console is output to UART3.)
My UART3 run at 115200 baud rate.
Why change M of DPLL4 will make my UART3 fail?
By AM37xx technical reference manual, UART3 is divided by PER_48M_FCLK not from DPLL4.
Could you please help?

Thanks a lot!
Mason