Part Number: TMS320C5517
Hello everybody,
we developed a board TMS320C5517 provided with 1,3V core and 3.3V I/O.
DSP power related schematics are attached.
We have a problem related to DSP LDO outputs (1V3_USB,1V3_SAR,1V3_CORE),
which on certain circustances simultaneously drop from the nominal level of 1,3V to about 1,0 V or less,
which is largely under specifications, and we believe could spoil the DSP.
First of all, in general what this voltage drop could mean ?
Which feature of the board could effect this internally generated voltages ?
Now here we explain the circumstances.
DSP is asynchronous EMIF interfaced to a FPGA, which in turn is the master for some slave ADCs.
When the FPGA is driving the ADCs control signal (MCLK,LRCLK,SCLK), as soon the ADCs are removed from Reset
all the DSP LCD outputs drop to 1,0 V or less: LCD outputs return to regular 1,3V as soon the ADCs are kept in Reset,
or the FPGA itself is kept in Reset.
The problem is also not present if we remove the ADCs from the board...
Please note that no direct digital HW interface exist between the ADCs and DSP; moreover in our tests,
we prevent DSP from driving the EMIF interface to FPGA.
Do not esitate to request us more informations.
Thank you for your attention.
