OMAP-L138: Cache MAR Bits

Keith Severy97

Part Number: OMAP-L138

On the DSP, do the MAR bits only control the caching for L2? or does it control L1 as well?

aka If don't enable the MAR bit (MAR128) for Shared Memory (0x80000000), and I have L1D & L2 caches enabled, does this memory range get cached into L1D?

over 8 years ago

0 Yordan Kovachev over 8 years ago

TI__Guru**** 161600 points

Hi Keith,

See DSP Megamodule Reference Guide (www.ti.com/.../sprufk5a.pdf). MAR registers are L2 Control registers. They enable caching for external memory regions. They enable caching for L1D and L2. This is further explained in Section 2.3 Cacheability of the DSP User Guide (www.ti.com/.../sprug82a.pdf):
"For L1D and L2, you can control whether external memory addresses are cacheable or noncacheable. Each external memory address space of 16M bytes is controlled by a memory attribute register (MAR) bit (0 = noncacheable, 1 = cacheable). "

But MAR registers are part of the L2 cache controller.

Best Regards,
Yordan

0 Keith Severy97 over 8 years ago in reply to Yordan Kovachev

Prodigy 50 points

Thanks a ton. That answers my question. It worried me that it was a L2 register, and I did not see that line in the user guide.

Thanks again.

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OMAP-L138: Cache MAR Bits