Linux/TDA2EG-17: Enter linux kernel QSPI operate speed just ~19MHz.

Tao Han

Part Number: TDA2EG-17

Tool/software: Linux

Hi Expert:

We find that visionsdk 2.12.02 the Linux operate QSPI speed setting at ~19Mhz.

At uboot we setting QSPI speed is 76.8MHz. (arch/arm/dts/dra71-evm.dts), probe the QSPI clock signal the speed is 76.8MHz.

But when kernel start, probe QSPI clock first it is 76.8MHz, when enter Linux console the QSPI read/write speed just 19MHz.

Default mode read 0x4b000040 it is 0x80000004.

use omapconf write 0x4b300040 0x80000001 change QSPI clock div from 4 to 1. the QSPI speed change to 76.8MHz at kernel.

Could you please help us check which part to code change the QSPI speed at kernel?

At DTS file we setting QSPI max speed is 76.8MHz, but we did not which part of code change the QSPI clock setting.

Best Regards!

Han Tao

over 7 years ago

0 Yordan Kamenov over 7 years ago

TI__Mastermind 42515 points

Hi,

I have forwarded your question to a QSPI expert for comment.

Regards,
Yordan

0 Ravikumar Kattekola over 7 years ago in reply to Yordan Kamenov

TI__Expert 4230 points

Hi,
 Is this on TI EVM or a custom board? 
Can you share the dts/dtsi files used for the board? 
For TI EVM arch/arm/boot/dts/dra72-evm-common.dtsi, both qspi and flash speed are set to 76.8MHz 
&qspi { 
status = "okay"; 

spi-max-frequency = <76800000>; 
m25p80@0 { 
compatible = "s25fl256s1"; 
spi-max-frequency = <76800000>; 

Do you have ismilar configuration? 

Regards,
RK

0 Tao Han over 7 years ago in reply to Ravikumar Kattekola

TI__Expert 6415 points

Hi RK:

Yes, the dts file setting QSPI interface and QSPI flash speed are 76.8MHz.

You can try run vision SDK 2.12.02 prebuild image. (tda2xx-evm/tisdk-rootfs-image-dra7xx-evm.tar.xz )

Test EVM board U18 pin 16, the clock is 19MHz.

If you use processor sdk 3.02 ()

file system. test U18 pin 16, the clock is 76.8MHz.

Believe Vision SDK has changed QSPI interface setting.

Test command root@dra7xx-evm:~# dd if=/dev/mtd6 of=/dev/null

Best Regards!

Han Tao

0 Ravi B over 7 years ago in reply to Tao Han

TI__Expert 7885 points

Han Tao

Can you please all DTS file you are using, what is the spi-max-frequency set to ?

Also please add debug prints in kernel ti-spi driver to check what is the exact value read from DTB file,

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 3f225f9..4968430 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -738,8 +738,10 @@ static int ti_qspi_probe(struct platform_device *pdev)
pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
pm_runtime_enable(&pdev->dev);

- if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
+ if (!of_property_read_u32(np, "spi-max-frequency", &max_freq)) {
+ printk("%s: spi-max-freq: %d\n", __func__, max_freq);
qspi->spi_max_frequency = max_freq;
+ }

ret = devm_spi_register_master(&pdev->dev, master);
if (ret)

Regards

Ravi

0 user4707998 over 7 years ago in reply to Ravi B

Prodigy 40 points

Fullscreen dra72-evm-common_dtsi.txt Download

/*
 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#define  DISPLAY_ON_A15_LINUX 0

#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>

/ {
	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";

	aliases {
		display0 = &lcd_fpd;
		sound0 = &snd0;
/*		sound1 = &hdmi;*/
	};

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	evm_5v0: fixedregulator-evm5v0 {
		/* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 1 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "evm_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 2 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	evm_3v3_sw: fixedregulator-evm_3v3 {
		/* TPS22965DSG */
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vsys_3v3>;
		regulator-always-on;
		regulator-boot-on;
	};

	aic_dvdd: fixedregulator-aic_dvdd {
		/* TPS77018DBVT */
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd";
		vin-supply = <&evm_3v3_sw>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	evm_3v3_sd: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3_sd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_3v3_sw>;
		enable-active-high;
/*		gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; */
	};

	extcon_usb1: extcon_usb1 {
		compatible = "linux,extcon-usb-gpio";
		vbus-gpio =/* <&pcf_lcd 14 GPIO_ACTIVE_HIGH>; */ <&gpio6 11 GPIO_ACTIVE_HIGH>;
	};

	extcon_usb2: extcon_usb2 {
		compatible = "linux,extcon-usb-gpio";
	};
#if DISPLAY_ON_A15_LINUX
	hdmi0: connector {
		compatible = "hdmi-connector";
		label = "hdmi";

		type = "a";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&tpd12s015_out>;
			};
		};
	};

	tpd12s015: encoder {
		compatible = "ti,tpd12s015";

		gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
			<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				tpd12s015_in: endpoint {
					remote-endpoint = <&hdmi_out>;
				};
			};

			port@1 {
				reg = <1>;

				tpd12s015_out: endpoint {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};
#else

#if 1 
/*	hdmi0: connector@1 {    */
    hdmi0: connector {
		compatible = "hdmi-connector";
		label = "hdmi";

		type = "a";
		hpd-gpios= <&gpio7 12 GPIO_ACTIVE_HIGH>;		/* gpio7_12/sp1_cs2, HPD */

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&hdmi_out>;
			};
		};
	};
#endif

#endif
	snd0: sound@0 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-EVM";
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack",
			"Line", "Line Out",
			"Microphone", "Mic Jack",
			"Line", "Line In";
		simple-audio-card,routing =
			"Headphone Jack",       "HPLOUT",
			"Headphone Jack",       "HPROUT",
			"Line Out",		"LLOUT",
			"Line Out",		"RLOUT",
			"MIC3L",		"Mic Jack",
			"MIC3R",		"Mic Jack",
			"Mic Jack",		"Mic Bias",
			"LINE1L",               "Line In",
			"LINE1R",               "Line In";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&sound0_master>;
		simple-audio-card,frame-master = <&sound0_master>;
		simple-audio-card,bitclock-inversion;

		sound0_master: simple-audio-card,cpu {
			sound-dai = <&mcasp3>;
			system-clock-frequency = <11289600>;
		};

		simple-audio-card,codec {
			sound-dai = <&tlv320aic3106>;
			clocks = <&atl_clkin2_ck>;
		};
	};

	vmmcwl_fixed: fixedregulator-mmcwl {
		compatible = "regulator-fixed";
		regulator-name = "vmmcwl_fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&dra7_pmx_core {
	mmc1_pins_default: mmc1_pins_default {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
		>;
	};

	mmc2_pins_default: mmc2_pins_default {
		pinctrl-single,pins = <
			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	dcan1_pins_default: dcan1_pins_default {
		pinctrl-single,pins = <
			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
			0x418   (PULL_UP | MUX_MODE1)	/* wakeup0.dcan1_rx */
		>;
	};

	dcan1_pins_sleep: dcan1_pins_sleep {
		pinctrl-single,pins = <
			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
		>;
	};

	wlan_pins: pinmux_wlan_pins {
		pinctrl-single,pins = <
			0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_ctsn.mmc4_clk */
			0x3ec (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_rtsn.mmc4_cmd */
			0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_rxd.mmc4_dat0 */
			0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_txd.mmc4_dat1 */
			0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_ctsn.mmc4_dat2 */
			0x3fc (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_rtsn.mmc4_dat3 */
			0x2cc (PIN_OUTPUT | MUX_MODE14)		/* mcasp1_axr6.gpio5_8 - WLAN_EN */
		>;
	};

	wlirq_pins: pinmux_wlirq_pins {
		pinctrl-single,pins = <
			0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */
		>;
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;
#if 0
	pcf_lcd: gpio@20 {
		compatible = "nxp,pcf8575";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	pcf_gpio_21: gpio@21 {
		compatible = "ti,pcf8575";
		reg = <0x21>;
		lines-initial-states = <0x1418>;
		gpio-controller;
		#gpio-cells = <2>;
	};
#endif
	tlv320aic3106: tlv320aic3106@19 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x19>;
		adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;		/* 2.0V */
		status = "okay";

		/* Regulators */
		AVDD-supply = <&evm_3v3_sw>;
		IOVDD-supply = <&evm_3v3_sw>;
		DRVDD-supply = <&evm_3v3_sw>;
	};
};

i2c_p3_exp: &i2c5 {
	status = "okay";
	clock-frequency = <400000>;
#if 0
	pcf_hdmi: pcf8575@26 {
		compatible = "nxp,pcf8575";
		reg = <0x26>;
		gpio-controller;
		#gpio-cells = <2>;
		/*
		 * initial state is used here to keep the mdio interface
		 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
		 * VIN2_S0 driven high otherwise Ethernet stops working
		 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
		 */
		lines-initial-states = <0x0f2b>;

		p1 {
			/* vin6_sel_s0: high: VIN6, low: audio */
			gpio-hog;
			gpios = <1 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "vin6_sel_s0";
		};
	};

	ov10633@37 {
		compatible = "ovti,ov10633";
		reg = <0x37>;

		mux-gpios = <&pcf_hdmi 2	GPIO_ACTIVE_HIGH>, /* VIN2_S0 */
			    <&pcf_hdmi 6	GPIO_ACTIVE_LOW>; /* VIN2_S2 */
		port {
			onboardLI: endpoint {
				remote-endpoint = <&vin2a>;
				hsync-active = <1>;
				vsync-active = <1>;
				pclk-sample = <0>;
			};
		};
	};

	gpio_csi2_adap: tca6416@20 {
		status = "okay";
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	ov490@24 {
		compatible = "ovti,ov490";
		reg = <0x24>;

		mux-gpios = <&gpio_csi2_adap 0	GPIO_ACTIVE_LOW>,
						/* CSI2_SEL_I2C_CLK */
			    <&gpio_csi2_adap 1	GPIO_ACTIVE_HIGH>,
						/* CSI2_SEL_REF_CLK */
			    <&gpio_csi2_adap 3	GPIO_ACTIVE_HIGH>,
						/* CSI2_CAM0_RESETn */
			    <&gpio_csi2_adap 4	GPIO_ACTIVE_LOW>;
						/* CSI2_CAM0_PWR_DWN */
		port {
			csi2_cam0: endpoint@0 {
				clock-lanes = <0>;
				data-lanes = <1 2 3 4>;
				remote-endpoint = <&csi2_phy0>;
			};
		};
	};
#endif
};

&uart1 {
	status = "okay";
	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
			      <&dra7_pmx_core 0x3e0>;
};

&uart3 {
	status = "okay";
};

&elm {
	status = "okay";
};

&gpmc {
	/*
	 * For the existing IOdelay configuration via U-Boot we don't
	 * support NAND on dra72-evm. Keep it disabled. Enabling it
	 * requires a different configuration by U-Boot.
	 */
	status = "disabled";
	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
	nand@0,0 {
		/* To use NAND, DIP switch SW5 must be set like so:
		 * SW5.1 (NAND_SELn) = ON (LOW)
		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
		 */
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;          /* device IO registers */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>; /* termcount */
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */	/* device IO registers */
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;
		gpmc,device-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <80>;
		gpmc,cs-wr-off-ns = <80>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <60>;
		gpmc,adv-wr-off-ns = <60>;
		gpmc,we-on-ns = <10>;
		gpmc,we-off-ns = <50>;
		gpmc,oe-on-ns = <4>;
		gpmc,oe-off-ns = <40>;
		gpmc,access-ns = <40>;
		gpmc,wr-access-ns = <80>;
		gpmc,rd-cycle-ns = <80>;
		gpmc,wr-cycle-ns = <80>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wait-monitoring-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <0>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x000020000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00020000 0x00020000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00040000 0x00020000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x00060000 0x00020000>;
		};
		partition@4 {
			label = "NAND.u-boot-spl-os";
			reg = <0x00080000 0x00040000>;
		};
		partition@5 {
			label = "NAND.u-boot";
			reg = <0x000c0000 0x00100000>;
		};
		partition@6 {
			label = "NAND.u-boot-env";
			reg = <0x001c0000 0x00020000>;
		};
		partition@7 {
			label = "NAND.u-boot-env.backup1";
			reg = <0x001e0000 0x00020000>;
		};
		partition@8 {
			label = "NAND.kernel";
			reg = <0x00200000 0x00800000>;
		};
		partition@9 {
			label = "NAND.file-system";
			reg = <0x00a00000 0x0f600000>;
		};
	};
};

&omap_dwc3_1 {
	extcon = <&extcon_usb1>;
};

&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
};

&usb1 {
	status = "okay";
	dr_mode = "host";
};

&usb2 {
	status = "disabled";
	dr_mode = "host";
};

&mmc1 {
	status = "okay";

	vmmc-supply = <&evm_3v3_sd>;
	bus-width = <4>;
	/*
	 * SDCD signal is not being used here - using the fact that GPIO mode
	 * is a viable alternative
	 */
	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
	max-frequency = <192000000>;
};

&mmc2 {
	/* SW5-3 in ON position */
	status = "okay";

	vmmc-supply = <&evm_3v3_sw>;
	bus-width = <8>;
	ti,non-removable;
	max-frequency = <192000000>;
};

&mmc4 {
	status = "okay";
	vmmc-supply = <&vmmcwl_fixed>;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&wlan_pins &wlirq_pins>;
	cap-power-off-card;
	keep-power-in-suspend;
	ti,non-removable;

	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@0 {
		compatible = "ti,wl1835";
		reg = <2>;
		interrupt-parent = <&gpio5>;
		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
	};
};

&mac {
	status = "okay";
};

&dcan1 {
	status = "ok";
	pinctrl-names = "default", "sleep", "active";
	pinctrl-0 = <&dcan1_pins_sleep>;
	pinctrl-1 = <&dcan1_pins_sleep>;
	pinctrl-2 = <&dcan1_pins_default>;
};

&qspi {
	status = "okay";

	spi-max-frequency = <76800000>;
	m25p80@0 {
		compatible = "n25q512ax3";
		spi-max-frequency = <76800000>;
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first four physical blocks
		 * for a valid file to boot and the flash here is
		 * 64KiB block size.
		 */
		partition@0 {
            label = "QSPI.SPL";
            reg = <0x00000000 0x00020000>;
        };
        partition@1 {
            label = "QSPI.dtb1";
            reg = <0x00020000 0x00020000>;
        };
        partition@2 {
            label = "QSPI.kernel1";
            reg = <0x00040000 0x00400000>;
        };
        partition@3 {
            label = "QSPI.cramfs";
            reg = <0x00440000 0x02300000>;
        }; 
        partition@4 {
            label = "QSPI.jffs2visionsdk";
            reg = <0x02740000 0x00A00000>;
        };
        partition@5 {
            label = "QSPI.dtb2";
            reg = <0x03140000 0x00020000>;
        };
        partition@6 {
            label = "QSPI.kernel2";
            reg = <0x03160000 0x00400000>;
        };
        partition@7 {
            label = "QSPI.minifs";
            reg = <0x03560000 0x00400000>;
        };
        partition@8 {
            label = "QSPI.updateflag";
            reg = <0x03FF0000 0x00010000>;
        };
	};
};
#if 0
&i2c5 {
	disp_ser: serializer@1b {
		compatible = "ti,ds90uh925q";
		reg = <0x1b>;

		#address-cells = <1>;
		#size-cells = <0>;
		ranges = <0x2c 0x2c>,
			<0x1c 0x1c>;

		disp_des: deserializer@2c {
			compatible = "ti,ds90uh928q";
			reg = <0x2c>;
			slave-mode;
		};
	};
};

&disp_ser {
	fpd_disp: tlc59108@1c {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "ti,tlc59108";
		reg = <0x1c>;

	};
};
#endif
/ {
	lcd_fpd: display_fpd {
		/*
		* This is not really a dpi panel, but panel-dpi driver
		* works as dummy panel driver.
		*/
		compatible = "lg,lp101wx2", "panel-dpi";

		label = "lcd_fpd";
		/* P0, SEL_GPMC_AD_VID_S0 */
		status = "okay";

		panel-timing {
			clock-frequency = <69300404>;
			hactive = <1280>;
			vactive = <800>;

			hfront-porch = <48>;
			hback-porch = <44>;
			hsync-len = <32>;

			vfront-porch = <4>;
			vback-porch = <7>;
			vsync-len = <12>;

			hsync-active = <0>;
			vsync-active = <0>;
			de-active = <1>;
			pixelclk-active = <0>;
		};

		port@lcd3 {
			fpd_in: endpoint {
				remote-endpoint = <&dpi_out3>;
			};
		};
	};
};

&dss {
	status = "ok";
	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		status = "okay";

		port@lcd3 {
			reg = <2>;

			dpi_out3: endpoint {
				remote-endpoint = <&fpd_in>;
				data-lines = <24>;
			};
		};
	};
};

&bb2d {
	status = "okay";
};
#if DISPLAY_ON_A15_LINUX
&hdmi {
	status = "disabled";

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&tpd12s015_in>;
		};
	};
};
#else
&hdmi {
	status = "disabled";

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&hdmi_connector_in>;
		};
	};
};
#endif
&vip1 {
	status = "okay";
};

video_in: &vin2a {
	status = "okay";
	endpoint@0 {
		slave-mode;
	};
};

&cal {
	status = "okay";
};

&csi2_0 {
	csi2_phy0: endpoint@0 {
		slave-mode;
	};
};

&atl {
	assigned-clocks = <&abe_dpll_sys_clk_mux>,
			  <&atl_gfclk_mux>,
			  <&dpll_abe_ck>,
			  <&dpll_abe_m2x2_ck>,
			  <&atl_clkin1_ck>,
			  <&atl_clkin2_ck>;
	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>,
			       <11289600>, <11289600>;

	status = "okay";

	atl2 {
		bws = <DRA7_ATL_WS_MCASP2_FSX>;
		aws = <DRA7_ATL_WS_MCASP3_FSX>;
	};
};

&mcasp3 {
	#sound-dai-cells = <0>;
	assigned-clocks = <&mcasp3_ahclkx_mux>;
	assigned-clock-parents = <&atl_clkin2_ck>;

	status = "okay";

	op-mode = <0>;          /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializer */
	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		status = "okay";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		status = "okay";
	};
};

&mailbox6 {
	status = "okay";
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
		status = "okay";
	};
};

&mmu0_dsp1 {
	status = "okay";
};

&mmu1_dsp1 {
	status = "okay";
};

&mmu_ipu1 {
	status = "okay";
};

&mmu_ipu2 {
	status = "okay";
};

&ipu2 {
	status = "okay";
	memory-region = <&ipu2_cma_pool>;
	mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
	timers = <&timer3>;
	watchdog-timers = <&timer4>, <&timer9>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_cma_pool>;
	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
	timers = <&timer11>;
	watchdog-timers = <&timer7>, <&timer8>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_cma_pool>;
	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
	timers = <&timer5>;
	watchdog-timers = <&timer10>;
};

&pcie1_rc {
	status = "okay";
};

Hi Ravi:

Please check attached dts file.

It is our board used one.

Best Regards!

Meng Xiang jian

0 Tao Han over 7 years ago in reply to user4707998

TI__Expert 6415 points

Fullscreen spilog.txt Download

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Initializing cgroup subsys cpuacct
[    0.000000] Linux version 4.4.45-00052-g0dcd1a3-dirty (changer@changer) (gcc version 5.3.1 20160113 (Linaro GCC 5.3-2016.02) ) #40 SMP PREEMPT Wed Dec 20 17:16:21 CST 2017
[    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] Machine model: TI DRA718 EVM
[    0.000000] Reserved memory: regions without no-map are not yet supported
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 80 MiB
[    0.000000] Reserved memory: initialized node ipu2_cma@95800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009e000000, size 32 MiB
[    0.000000] Reserved memory: initialized node ipu1_cma@9d000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: regions without no-map are not yet supported
[    0.000000] Reserved memory: created CMA memory pool at 0x00000000a1000000, size 32 MiB
[    0.000000] Reserved memory: initialized node dsp1_cma@99000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a9000000, size 64 MiB
[    0.000000] Reserved memory: initialized node cmem@A9000000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x00000000be400000
[    0.000000] Forcing write-allocate cache policy for SMP
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] OMAP4: Map 0x00000000bfd00000 to fe600000 for dram barrier
[    0.000000] DRA722 ES2.0
[    0.000000] PERCPU: Embedded 11 pages/cpu @ef648000 s14848 r8192 d22016 u45056
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 243264
[    0.000000] Kernel command line: console=ttyO0,115200n8 vram=16M root=PARTUUID=1ad61f8d-02 rw rootwait ip=none mem=1024M
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 427188K/979968K available (6627K kernel code, 371K rwdata, 2492K rodata, 332K init, 290K bss, 380748K reserved, 172032K cma-reserved, 234496K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc08f0044   (9121 kB)
[    0.000000]       .init : 0xc08f1000 - 0xc0944000   ( 332 kB)
[    0.000000]       .data : 0xc0944000 - 0xc09a0fd0   ( 372 kB)
[    0.000000]        .bss : 0xc09a2000 - 0xc09ea880   ( 291 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  Build-time adjustment of leaf fanout to 32.
[    0.000000]  RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=1
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] ti_dt_clocks_register: failed to lookup clock node gmac_gmii_ref_clk_div
[    0.000000] OMAP clockevent source: timer1 at 32786 Hz
[    0.000000] Architected cp15 timer(s) running at 6.14MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[    0.000006] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
[    0.000019] Switching to timer-based delay loop, resolution 162ns
[    0.000417] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000427] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000959] Console: colour dummy device 80x30
[    0.000978] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
[    0.000986] This ensures that you still see kernel messages. Please
[    0.000994] update your kernel commandline.
[    0.001009] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
[    0.001025] pid_max: default: 32768 minimum: 301
[    0.001139] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001152] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001797] Initializing cgroup subsys io
[    0.001816] Initializing cgroup subsys memory
[    0.001845] Initializing cgroup subsys devices
[    0.001862] Initializing cgroup subsys freezer
[    0.001876] Initializing cgroup subsys perf_event
[    0.001891] Initializing cgroup subsys pids
[    0.001924] CPU: Testing write buffer coherency: ok
[    0.002159] /cpus/cpu@0 missing clock-frequency property
[    0.002174] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.002216] Setting up static identity map for 0x80008380 - 0x800083e0
[    0.050010] Brought up 1 CPUs
[    0.050024] SMP: Total of 1 processors activated (12.29 BogoMIPS).
[    0.050033] CPU: All CPU(s) started in HYP mode.
[    0.050040] CPU: Virtualization extensions available.
[    0.050408] devtmpfs: initialized
[    0.090037] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[    0.091227] omap_hwmod: l3_main_2 using broken dt data from ocp
[    0.206903] omap_hwmod: vpe: no dt node
[    0.206916] ------------[ cut here ]------------
[    0.206935] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2523 _init.constprop.23+0x200/0x428()
[    0.206944] omap_hwmod: vpe: doesn't have mpu register target base
[    0.206951] Modules linked in:
[    0.206969] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.45-00052-g0dcd1a3-dirty #40
[    0.206978] Hardware name: Generic DRA72X (Flattened Device Tree)
[    0.206986] Backtrace:
[    0.207012] [<c00131b8>] (dump_backtrace) from [<c00133b4>] (show_stack+0x18/0x1c)
[    0.207021]  r7:c08fe01c r6:60000013 r5:00000000 r4:c0970e0c
[    0.207057] [<c001339c>] (show_stack) from [<c02b4e0c>] (dump_stack+0x8c/0xa0)
[    0.207073] [<c02b4d80>] (dump_stack) from [<c0034f6c>] (warn_slowpath_common+0x88/0xb8)
[    0.207081]  r7:c08fe01c r6:000009db r5:00000009 r4:ef06fe58
[    0.207108] [<c0034ee4>] (warn_slowpath_common) from [<c0034fd4>] (warn_slowpath_fmt+0x38/0x40)
[    0.207116]  r8:000000ab r7:ef1a4c80 r6:00000000 r5:00000000 r4:c0825800
[    0.207148] [<c0034fa0>] (warn_slowpath_fmt) from [<c08fe01c>] (_init.constprop.23+0x200/0x428)
[    0.207156]  r3:c0827ae0 r2:c0825800
[    0.207169]  r4:c0954e98
[    0.207185] [<c08fde1c>] (_init.constprop.23) from [<c08fe374>] (__omap_hwmod_setup_all+0x48/0x98)
[    0.207192]  r10:00000000 r9:c08f1600 r8:000000ab r7:ef1a4c80 r6:c09496b0 r5:c094bb38
[    0.207220]  r4:c0954e98
[    0.207236] [<c08fe32c>] (__omap_hwmod_setup_all) from [<c000982c>] (do_one_initcall+0x98/0x1e4)
[    0.207244]  r5:c08fe32c r4:c09496b0
[    0.207264] [<c0009794>] (do_one_initcall) from [<c08f1f68>] (kernel_init_freeable+0x1d4/0x268)
[    0.207272]  r10:00000002 r9:c08f1600 r8:000000ab r7:c0931820 r6:c093eff4 r5:c09a2000
[    0.207299]  r4:c09a2000
[    0.207318] [<c08f1d94>] (kernel_init_freeable) from [<c0679d04>] (kernel_init+0x18/0xf4)
[    0.207326]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c0679cec
[    0.207352]  r4:c09a2000
[    0.207369] [<c0679cec>] (kernel_init) from [<c000fb88>] (ret_from_fork+0x14/0x2c)
[    0.207377]  r5:c0679cec r4:00000000
[    0.207404] ---[ end trace f7236bd7202eddff ]---
[    0.209913] omap_hwmod: wd_timer2: no dt node
[    0.209921] ------------[ cut here ]------------
[    0.209935] WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2523 _init.constprop.23+0x200/0x428()
[    0.209943] omap_hwmod: wd_timer2: doesn't have mpu register target base
[    0.209949] Modules linked in:
[    0.209965] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W       4.4.45-00052-g0dcd1a3-dirty #40
[    0.209973] Hardware name: Generic DRA72X (Flattened Device Tree)
[    0.209979] Backtrace:
[    0.210000] [<c00131b8>] (dump_backtrace) from [<c00133b4>] (show_stack+0x18/0x1c)
[    0.210008]  r7:c08fe01c r6:60000013 r5:00000000 r4:c0970e0c
[    0.210039] [<c001339c>] (show_stack) from [<c02b4e0c>] (dump_stack+0x8c/0xa0)
[    0.210053] [<c02b4d80>] (dump_stack) from [<c0034f6c>] (warn_slowpath_common+0x88/0xb8)
[    0.210060]  r7:c08fe01c r6:000009db r5:00000009 r4:ef06fe58
[    0.210087] [<c0034ee4>] (warn_slowpath_common) from [<c0034fd4>] (warn_slowpath_fmt+0x38/0x40)
[    0.210095]  r8:000000ab r7:ef1a4c80 r6:00000000 r5:00000000 r4:c0825800
[    0.210125] [<c0034fa0>] (warn_slowpath_fmt) from [<c08fe01c>] (_init.constprop.23+0x200/0x428)
[    0.210133]  r3:c0824b20 r2:c0825800
[    0.210146]  r4:c0950018
[    0.210161] [<c08fde1c>] (_init.constprop.23) from [<c08fe374>] (__omap_hwmod_setup_all+0x48/0x98)
[    0.210169]  r10:00000000 r9:c08f1600 r8:000000ab r7:ef1a4c80 r6:c09496b0 r5:c094bb38
[    0.210196]  r4:c0950018
[    0.210211] [<c08fe32c>] (__omap_hwmod_setup_all) from [<c000982c>] (do_one_initcall+0x98/0x1e4)
[    0.210219]  r5:c08fe32c r4:c09496b0
[    0.210238] [<c0009794>] (do_one_initcall) from [<c08f1f68>] (kernel_init_freeable+0x1d4/0x268)
[    0.210245]  r10:00000002 r9:c08f1600 r8:000000ab r7:c0931820 r6:c093eff4 r5:c09a2000
[    0.210271]  r4:c09a2000
[    0.210288] [<c08f1d94>] (kernel_init_freeable) from [<c0679d04>] (kernel_init+0x18/0xf4)
[    0.210295]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c0679cec
[    0.210320]  r4:c09a2000
[    0.210337] [<c0679cec>] (kernel_init) from [<c000fb88>] (ret_from_fork+0x14/0x2c)
[    0.210345]  r5:c0679cec r4:00000000
[    0.210378] ---[ end trace f7236bd7202ede00 ]---
[    0.319067] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.324804] pinctrl core: initialized pinctrl subsystem
[    0.325855] NET: Registered protocol family 16
[    0.327010] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.350591] cpuidle: using governor ladder
[    0.380618] cpuidle: using governor menu
[    0.391429] OMAP GPIO hardware version 0.1
[    0.399242] irq: no irq domain found for /ocp/l4@4a000000/scm@2000/pinmux@1400 !
[    0.426885] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[    0.426898] hw-breakpoint: maximum watchpoint size is 8 bytes.
[    0.427488] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[    0.427500] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[    0.428203] OMAP DMA hardware revision 0.0
[    0.513978] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[    0.515388] edma 43300000.edma: memcpy is disabled
[    0.521247] edma 43300000.edma: TI EDMA DMA engine driver
[    0.527155] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[    0.527388] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[    0.527603] omap-iommu 58882000.mmu: 58882000.mmu registered
[    0.527808] omap-iommu 55082000.mmu: 55082000.mmu registered
[    0.531655] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
[    0.532193] omap_i2c 48060000.i2c: bus 2 rev0.12 at 400 kHz
[    0.551127] pca953x 4-0020: failed reading register
[    0.551152] pca953x: probe of 4-0020 failed with error -121
[    0.551756] mcp230xx: probe of 4-0027 failed with error -121
[    0.552084] mcp230xx: probe of 4-0021 failed with error -121
[    0.552411] mcp230xx: probe of 4-0025 failed with error -121
[    0.553318] omap_i2c 4807c000.i2c: bus 4 rev0.12 at 400 kHz
[    0.553541] media: Linux media interface: v0.10
[    0.553603] Linux video capture interface: v2.00
[    0.553655] pps_core: LinuxPPS API ver. 1 registered
[    0.553663] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.553691] PTP clock support registered
[    0.553743] EDAC MC: Ver: 3.0.0
[    0.561727] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[    0.561985] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
[    0.562401] Advanced Linux Sound Architecture Driver Initialized.
[    0.563463] clocksource: Switched to clocksource arch_sys_counter
[    0.575909] NET: Registered protocol family 2
[    0.576522] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    0.576602] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[    0.576758] TCP: Hash tables configured (established 8192 bind 8192)
[    0.576819] UDP hash table entries: 512 (order: 2, 16384 bytes)
[    0.576857] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[    0.577111] NET: Registered protocol family 1
[    0.587471] RPC: Registered named UNIX socket transport module.
[    0.587483] RPC: Registered udp transport module.
[    0.587492] RPC: Registered tcp transport module.
[    0.587500] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.588706] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
[    0.591590] futex hash table entries: 256 (order: 2, 16384 bytes)
[    0.611114] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.621944] NFS: Registering the id_resolver key type
[    0.621978] Key type id_resolver registered
[    0.621987] Key type id_legacy registered
[    0.622069] ntfs: driver 2.1.32 [Flags: R/O].
[    0.624870] bounce: pool size: 64 pages
[    0.625074] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[    0.625095] io scheduler noop registered
[    0.625113] io scheduler deadline registered
[    0.625157] io scheduler cfq registered (default)
[    0.630167] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[    0.630365] pinctrl-single 4a002e8c.pinmux: 1 pins at pa fc002e8c size 4
[    0.634227] PCI host bridge /ocp/axi@0/pcie_rc@51000000 ranges:
[    0.634244]   No bus range found for /ocp/axi@0/pcie_rc@51000000, using [bus 00-ff]
[    0.634286]    IO 0x20003000..0x20012fff -> 0x00000000
[    0.634313]   MEM 0x20013000..0x2fffffff -> 0x20013000
[    0.666133] dra7-pcie 51000000.pcie_rc: link is not up
[    0.666341] dra7-pcie 51000000.pcie_rc: PCI host bridge to bus 0000:00
[    0.666356] pci_bus 0000:00: root bus resource [bus 00-ff]
[    0.666369] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    0.666382] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[    0.666882] PCI: bus0: Fast back to back transfers disabled
[    0.667035] PCI: bus1: Fast back to back transfers enabled
[    0.667146] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff]
[    0.667165] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff]
[    0.667181] pci 0000:00:00.0: PCI bridge to [bus 01]
[    0.667461] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt
[    0.737648] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[    0.741721] 4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 301, base_baud = 3000000) is a 8250
[    2.104212] console [ttyS0] enabled
[    2.108832] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 302, base_baud = 3000000) is a 8250
[    2.119105] [drm] Initialized drm 1.1.0 20060810
[    2.125103] vsys_3v3: supplied by evm_12v0
[    2.129268] evm_3v3: supplied by vsys_3v3
[    2.133342] aic_dvdd: supplied by evm_3v3
[    2.137669] OMAP DSS rev 6.1
[    2.141618] omapdss_dss 58000000.dss: bound 58001000.dispc (ops dispc_component_ops)
[    2.239307] loop: module loaded
[    2.257596] vmemexp device MAJOR num = 246
[    2.261731] vmemexp class registered
[    2.265492] /dev/vmemexp device registered
[    2.269608] ioctl DBUFIOC_EXPORT_VIRTMEM = -1072899120
[    2.277095] ti_qspi_probe: spi-max-freq: 76800000
[    2.282538] m25p80 spi32766.0: n25q512ax3 (65536 Kbytes)
[    2.288016] 9 ofpart partitions found on MTD device spi32766.0
[    2.293896] Creating 9 MTD partitions on "spi32766.0":
[    2.299060] 0x000000000000-0x000000020000 : "QSPI.SPL"
[    2.315392] 0x000000020000-0x000000040000 : "QSPI.dtb1"
[    2.331760] 0x000000040000-0x000000440000 : "QSPI.kernel1"
[    2.348429] 0x000000440000-0x000002740000 : "QSPI.cramfs"
[    2.364998] 0x000002740000-0x000003140000 : "QSPI.jffs2visionsdk"
[    2.382241] 0x000003140000-0x000003160000 : "QSPI.dtb2"
[    2.398662] 0x000003160000-0x000003560000 : "QSPI.kernel2"
[    2.415295] 0x000003560000-0x000003960000 : "QSPI.minifs"
[    2.431805] 0x000003ff0000-0x000004000000 : "QSPI.updateflag"
[    2.449930] libphy: Fixed MDIO Bus: probed
[    2.503501] davinci_mdio 48485000.mdio: davinci mdio revision 1.6
[    2.509629] davinci_mdio 48485000.mdio: no live phy, scanning all
[    2.613464] davinci_mdio 48485000.mdio: timed out waiting for user access
[    2.713462] davinci_mdio 48485000.mdio: timed out waiting for idle
[    2.719698] davinci_mdio: probe of 48485000.mdio failed with error -5
[    2.726696] cpsw 48484000.ethernet: No slave[0] phy_id, phy-handle, or fixed-link property
[    2.735055] cpsw 48484000.ethernet: No slave[1] phy_id, phy-handle, or fixed-link property
[    2.743380] cpsw 48484000.ethernet: Detected MACID = 64:cf:d9:55:37:6c
[    2.750104] cpsw 48484000.ethernet: cpts: overflow check period 800
[    2.758624] mousedev: PS/2 mouse device common for all mice
[    2.775257] i2c /dev entries driver
[    2.779605] ov1063x 4-0037: Failed writing register 0x0103!
[    2.785276] ov1063x: probe of 4-0037 failed with error -121
[    2.791204] ov1063x 4-0030: Failed writing register 0x0103!
[    2.796839] ov1063x: probe of 4-0030 failed with error -121
[    2.802691] ov490 4-0024: Failed reading register 0x300a!
[    2.808145] ov490: probe of 4-0024 failed with error -121
[    2.819432] omap_hsmmc 4809c000.mmc: Got CD GPIO
[    2.824519] evm_3v3_sd: supplied by evm_3v3
[    2.874047] omap_hsmmc 480b4000.mmc: no pinctrl state for sdr25 mode
[    2.880437] omap_hsmmc 480b4000.mmc: no pinctrl state for sdr12 mode
[    2.933921] omap_hsmmc 480d1000.mmc: no pinctrl state for sdr25 mode
[    2.940309] omap_hsmmc 480d1000.mmc: no pinctrl state for sdr12 mode
[    2.963470] omap_hsmmc 480d1000.mmc: no pinctrl state for hs mode
[    3.004392] ledtrig-cpu: registered to indicate activity on CPUs
[    3.024578] 0-0019 supply DVDD not found, using dummy regulator
[    3.045384] NET: Registered protocol family 10
[    3.063892] sit: IPv6 over IPv4 tunneling driver
[    3.069211] NET: Registered protocol family 17
[    3.083739] Key type dns_resolver registered
[    3.088168] omap_voltage_late_init: Voltage driver support not added
[    3.104168] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.oppdm
[    3.110380] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.oppdm
[    3.133490] cpu0 supply vdd not found, using dummy regulator
[    3.139496] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.oppdm
[    3.163512] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.oppdm
[    3.169739] cpu0 supply vdd not found, using dummy regulator
[    3.184513] Power Management for TI OMAP4+ devices.
[    3.189688] Registering SWP/SWPB emulation handler
[    3.214842] dmm 4e000000.dmm: initialized all PAT entries
[    3.232486] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    3.239218] [drm] No driver support for vblank timestamp query.
[    3.246094] [drm] Initialized omapdrm 1.0.0 20110917 on minor 0
[    3.272847] evm_5v0: supplied by evm_12v0
[    3.277003] lp8733-ldo1: supplied by evm_5v0
[    3.286275] asoc-simple-card sound@0: tlv320aic3x-hifi <-> 48468000.mcasp mapping ok
[    3.295971] mmc0: host does not support reading read-only switch, assuming write-enable
[    3.307870] hctosys: unable to open rtc device (rtc0)
[    3.314598] mmc0: new high speed SDHC card at address 1234
[    3.335359] aic_dvdd: disabling
[    3.338796] ALSA device list:
[    3.341777]   #0: DRA7xx-EVM
[    3.345465] mmcblk0: mmc0:1234 SA08G 7.21 GiB
[    3.351728]  mmcblk0: p1 p2
[    3.358277] EXT4-fs (mmcblk0p2): couldn't mount as ext3 due to feature incompatibilities
[    3.368308] EXT4-fs (mmcblk0p2): couldn't mount as ext2 due to feature incompatibilities
[    3.431913] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[    3.440122] VFS: Mounted root (ext4 filesystem) on device 179:2.
[    3.450560] devtmpfs: mounted
[    3.453826] Freeing unused kernel memory: 332K (c08f1000 - c0944000)
[    3.460209] This architecture does not have kernel memory protection.
INIT: version 2.88 booting
===== sysfs time: 3
Starting udev:  3
Starting udev
udev: using cache file /etc/dev.tar
[    3.931414] udevd[93]: starting version 3.1.5
[    3.938015] random: udevd: uninitialized urandom read (16 bytes read, 7 bits of entropy available)
[    4.046721] random: udevd: uninitialized urandom read (16 bytes read, 8 bits of entropy available)
Starting udev done
INIT: Entering runlevel: 5
modprobe: can't change directory to '4.4.45-00052-g0dcd1a3-dirty': No such file or directory
Module pvrsrvkm failed to load. Retrying.
modprobe: can't change directory to '4.4.45-00052-g0dcd1a3-dirty': No such file or directory
done========================
[    5.362265] memcache: module_layout: kernel tainted.
[    5.367440] Disabling lock debugging due to kernel taint
[    5.372783] memcache: version magic '4.4.45+ SMP preempt mod_unload ARMv7 p2v8 ' should be '4.4.45-00052-g0dcd1a3-dirty SMP preempt mod_unload modversions ARMv7 p2v8 '
insmod: can't insert './bin/memcache.ko': invalid module format
start demo.out

Hi Ravi:

Please check the log. customer board print out QSPI speed is 76.8MHz.

Best Regards!

Han Tao

[    2.269608] ioctl DBUFIOC_EXPORT_VIRTMEM = -1072899120
[    2.277095] ti_qspi_probe: spi-max-freq: 76800000
[    2.282538] m25p80 spi32766.0: n25q512ax3 (65536 Kbytes)
[    2.288016] 9 ofpart partitions found on MTD device spi32766.0

0 Ravi B over 7 years ago in reply to Tao Han

TI__Expert 7885 points

Han Tao

Yes, the spi-max-frequency passed from DTB is correct. Would like to know what is the clk_divider value configured in QSPI_CLOCK_CNTRL_REG (0x4b300040).

Can you add the below debug prints as well to check the clk_div value configured .

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 3f225f9..224de49 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -162,6 +162,8 @@ static int ti_qspi_setup(struct spi_device *spi)
clk_rate = clk_get_rate(qspi->fclk);

clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
+ printk("%s: clk_rate(%d), clk_div(%x),spi_max_frquency(%d)\n", __func__, clk_rate, clk_div,
+ qspi->spi_max_frequency);

if (clk_div < 0) {
dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
@@ -194,6 +196,8 @@ static int ti_qspi_setup(struct spi_device *spi)
clk_mask = QSPI_CLK_EN | clk_div;
ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
ctx_reg->clkctrl = clk_mask;
+ printk("%s: clk_mask(%x) clock_ctrl_reg(%x)\n", __func__, clk_mask,
+ ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG));

pm_runtime_mark_last_busy(qspi->dev);
ret = pm_runtime_put_autosuspend(qspi->dev);
@@ -738,8 +742,10 @@ static int ti_qspi_probe(struct platform_device *pdev)
pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
pm_runtime_enable(&pdev->dev);

- if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
+ if (!of_property_read_u32(np, "spi-max-frequency", &max_freq)) {
+ printk("%s: spi-max-freq: %d\n", __func__, max_freq);
qspi->spi_max_frequency = max_freq;
+ }

ret = devm_spi_register_master(&pdev->dev, master);
if (ret)

Regards

Ravi

0 user4707998 over 7 years ago in reply to Ravi B

Prodigy 40 points

Hi Ravi:

Please check below print out log.

0x4b300040 setting is 0x8000000.

We find that vision sdk change 0x4a009838 register.

omapconf read 0x4a009838 the value is 0x05030002.

If we change 0x4a009839 to 0x01030002, the QSPI read speed change to 76.8MHz.

best regards!

Meng xiang jian

1.754404] aic_dvdd: supplied by evm_3v3
[ 1.758643] OMAP DSS rev 6.1
[ 1.762582] omapdss_dss 58000000.dss: bound 58001000.dispc (ops 0xc04607b4)
[ 1.856297] loop: module loaded
[ 1.876708] vmemexp device MAJOR num = 246
[ 1.880846] vmemexp class registered
[ 1.884613] /dev/vmemexp device registered
[ 1.888729] ioctl DBUFIOC_EXPORT_VIRTMEM = -1072899120
[ 1.895045] ti_qspi_probe: spi-max-freq: 76800000
[ 1.900165] ti_qspi_setup: clk_mask(80000000) clock_ctrl_reg(80000000)
[ 1.907182] m25p80 spi32766.0: n25q512ax3 (65536 Kbytes)
[ 1.922932] 9 ofpart partitions found on MTD device spi32766.0
[ 1.928795] Creating 9 MTD partitions on "spi32766.0":
[ 1.934018] 0x000000000000-0x000000020000 : "QSPI.SPL"

0 Ravi B over 7 years ago in reply to user4707998

TI__Expert 7885 points

Hi Meng Xiang Jian

Ok, after setting CM_L4PER2_QSPI_CLKCTRL.CLKSEL_DEV to right value (divide by 1), you are able to get 76.8Mhz.

Regards

Ravi

0 Tao Han over 7 years ago in reply to Ravi B

TI__Expert 6415 points

Hi Ravi:

Yes. Change CM_L4PER2_QSPI_CLKCTRL.CLKSEL_DEV can use 76.8Mhz read QSPI.

But we did not know whether code modified those register.

Just find dts have descript about those register. Uboot those register is divide by 1, but kernel it divide by 4.

Best Regards!

Han Tao

0 Ravi B over 7 years ago in reply to Tao Han

TI__Expert 7885 points

Han Tao

The U-BOOT or kernel is NOT configuring the CM_L4PER2_QSPI_CLKCTRL.CLKSEL_DEV bits.
The default value is 0, it means to provide maximum clock frequency, internally the qspi driver QSPI_CLOCK_CNTL_REG used to divide the clock based on desired value.

Reference in kernel for this register is clock dtsi file @ arch/arm/boot/dts/dra7xx-clocks.dtsi.

qspi_gfclk_div: qspi_gfclk_div {

#clock-cells = <0>;

compatible = "ti,divider-clock";

clocks = <&qspi_gfclk_mux>;

ti,bit-shift = <25>;

ti,max-div = <4>;

reg = <0x1838>;

ti,index-power-of-two;

};

In u-boot: CLOCK_SOURCE is selected as 1 (PER_QSPI_CLK from DPLL_PER)

arch/arm/cpu/armv7/omap5/hw_data.c

void enable_basic_clocks(void)

{

…

#ifdef CONFIG_TI_QSPI

setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));

#endif

}

I assume in your SPL code, some where the bit 26:25 of CM_L4PER2_QSPI_CLKCTRL.CLKSEL_DEV has been set to 4.

Regards

Ravi

0 Tao Han over 7 years ago in reply to Ravi B

TI__Expert 6415 points

Hi Ravi:

It is vision SDK IPU firmware change QSPI speed to 19.2Mhz.

change utils-prcm.c line 427. setting CM_L4PER2_QSPI_CLKCTRL to 0x01000000.

then we can use 76.8MHz access QSPI.

Best Regards!

Han Tao

prcm_set_module_mode(L4PER_CM_CORE, L4PER_CM_CORE__CM_L4PER2_QSPI_CLKCTRL, MODE_ENABLED, 0x05000000, 0x07000000 );

Processors

Processors forum

Linux/TDA2EG-17: Enter linux kernel QSPI operate speed just ~19MHz.