EVMC6474 DDR/L2/L1 read/write latency

There are several interesting Application Notes that you can read for the TMS320C6474. If you go to the TMS320C6474 Product Folder (click on the part number in this post) and click on Technical Documents, you will find several Application Notes. User's Guide follow after that.

In particular, look for the Application Note titled "TMS320C6474 Module Throughput Application Report" for information on through rates with different peripherals.

Throughput is the constraint that we designed the internal buses, peripherals, and controllers for. Latency is not generally measured in these reports. For high-performance DSP algorithms, the time from starting a DSP algorithm to ending that algorithm is what we strive to minimize, and not the time to do a single step within it.

Also, please keep in mind that whenever you are moving blocks of data or even accessing blocks of data, the EDMA3 and IDMA0/1 resources provide "parallel processing" for your algorithm if you are able to architect your system or application to make use of multiple resources simultaneously.

In the Training section of TI.com, there is a training video set for the C6474. It may be helpful for you to review all of the modules. But in particular, the Memory and Cache Module will apply to your current questions. You can find the complete video set at http://focus.ti.com/docs/training/catalog/events/event.jhtml?sku=OLT110002 .

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