TMS320C5545: TMS320C5545* FLASH INTERFACE

Hi Eli,

I am not sure that the parallel speeds can be achieved with a serial memory interface.
Comparing bandwitdhs can be a laborious process, which I was hoping had been published on a TI wiki page someplace already. Not being able to find it, I took a stab at some back of the envelope calculations...

Couple questions:
1) Is the customer booting from these memories? The bootloader has default clock configurations and sometimes lacks configurability to speed up accesses, but some knobs can be turned to improve copy rates.
2) What measured throughput are they achieving with the parallel memory today?

EMIF vs SPI

It is easiest to calculate the peak theoretical throughput. But we know that the actual throughput will be much lower (caused by software overhead, protocol overhead, and access latencies). In some cases software overhead can be reduced by using the DMA (depending on availability). On C55xx, the SPI peripheral is not connected to any DMA (except C5517 McSPI, which does support DMA).

I will use Megabits per second (Mbps) to capture throughput.

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EMIF
Theoretical maximum
16 bits per cycle x 100MHz (cyles per sec) = 1600Mbps (theoretical maximum, during burst read)

Bandwidth is cut down for reading non-sequential addresses as the memory requires the 70ns access time for each read plus about one cycle of turnaround time between accesses.
70ns access time from address/CE going active + 10ns Bus turn around = 80ns cycle (12.5MHz)
16 bits per cycle x 12.5MHz works out to 200Mbps

Reading multiple short bursts of words sequentially from non-sequential addresses can provide bandwidth in between these extremes.

Reading a 4-word burst from non-sequential addresses
70ns access time for first word, then 10ns for each additional three words, followed by 10ns bus turnaround = 110ns cycle (9.1MHz)
4 x 16 bits per cycle x 9.1MHz works out to 581Mbps

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SPI

Theoretical maximum
1 bit per cycle (serial) x 25MHz (cyles per sec) = 25Mbps (theoretical maximum during fast read command, ignoring command, address, software overhead)

Bandwidth is cut down for reading non-sequential addresses. SPI memory requires an 8-bit command + 24-bit address to receive 16-bit data (all serialized) = 48 cycles to get 16-bits of data.
At 25MHz, 8.3Mbps

Again reading short bursts of words sequentially from non-sequential addresses delivers bandwidth between the extremes.

We have mesured copy rates on C5545 of 12Mbps (reading 32 bits per access instead of 16, no DMA available)

Other devices might be able to utilize the SPI sequential read mode (where limitless sequential words are read without issuing a new command and address (saving 32-cycles per 16-bit word).

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Anyway, working backwards from 16-bit EMIF @ 100MHz, we can calculate the clock frequency required to get the same throughput with a 1-bit SPI...

To match the 1600Mbps theoretical maximum with parallel memory interface, the SPI CLK would have to run at 1600 MHz, (utilizing fast read / sequential read) - this is not possible.

Reading from non-sequential addresses, we must supply the command and address each time. To match the 200Mbps performance of a parallel memory the SPI CLK must be 600MHz, which is also not possible.

Enter Quad SPI and Octal SPI. These memories parallelize the serial protocol with 4 or 8 data lines instead of one.

Quad SPI on AM572x delivers 4 bits per cycle (quad serial) x 76.8MHz (AM572x max rate) = 307.2Mbps

The Micron MT25Q QSPI can run upto 166MHz
4 bits per cycle (quad serial) x 166MHz (cyles per sec) = 664Mbps

Again, reaching these theoretical maximum rates is not possible. The actual rate is lower.

An octal SPI like the Micron Xccela memory (x8 @ 200MHz) delivers 400MBytes/sec (3200Mbps) by launching x8 data on both clock edges (double data rate). I believe some Quad SPI devices support double data rate, but I am not aware that TI processors can handle it.

Note: PLL frequencies and integer dividers may force you to run at slower clock frequency than the fastest frequency published in the timing tables of the datasheet.

Hope this helps you find what you are looking for.

- Mark