Part Number: TDA2SG
Tool/software: Code Composer Studio
As we know the TDA2x has L3 on-chip memory.
We also see a l3Memsize setting in TIDL (tidl_tb.c):
*******************************************************************************
createParams.l1MemSize = DMEM0_SIZE;
createParams.l2MemSize = DMEM1_SIZE;
createParams.l3MemSize = OCMC_SIZE;
*******************************************************************************
I found the memory allocation to L1, L2, but I didn't see any allocation to L3 cache buffer.
Is the L3 usage already implemented in TIDL (both EVE and DSP) ?
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#pragma DATA_SECTION (DMEM0_SCRATCH, ".dmem0Sect");
uint8_t DMEM0_SCRATCH[DMEM0_SIZE];
#pragma DATA_SECTION (DMEM1_SCRATCH, ".dmem1Sect");
uint8_t DMEM1_SCRATCH[DMEM1_SIZE];
********************************************************************************
Charles
