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TMS320C6713 EMIF to FPGA

DanR
Prodigy 240 points
Other Parts Discussed in Thread: TMS320C6713B

Hi,

My cusotmer is working on an FPGA DMA interface between the FPGA SRAM and the TMS320C6713B EMIF. They have SRAM inside the FPGA. They would like to use the DSP's SBSRAM.

“TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide” page 56~57 show SBSRAM Read and SBSRAM Write for C670x EMIF and page 84~85 show SBSRAM Read and SBSRAM Write for C671x. The difference is with the former SBSRAM style, the DSP will generate address and with the latter SBSRAM style, the FPGA will generate address. They prefer to let the DSP generate the address, but they are using the C6713. It seems that they have to let the FPGA generate the address. Is this correct?

Why do these two DSPs have different SBSRAM styles? What is the advantage to let the FPGA generate address?

Thanks!

Dan

 

  • 0
    TI__Expert 8785 points

    I compared the EMIF and saw that the address pins are outputs in both interfaces, so the DSP should be driving the address lines.  Can you let me know where you saw the reference that SRAM will generate the address?

    --Christina

  • 0 in reply to clam
    Prodigy 240 points

    Thanks for the response. I agree that Figure 3-2 shows the address as output of DSP. Next page Table 3-1 also says “External Address Output”.

     

    Here are my customer's thoughts - "I guess maybe the address is just starting address. For example, each DMA burst transfer will exchange 100 words, DSP generates the starting address. The SRAM will generate sub-address for the 100 words. That means once my FPGA receives the starting address and enable signal, FPGA will put 100 words on the bus at clock DSP provides".

    Is my customer's understanding correct?

    Thanks!

    Dan

  • 0 in reply to DanR
    TI__Expert 8785 points

    Table 1-8 gives a good comparison of the SBSRAM interface between the devices. Based on my understanding of the C671x EMIF SBSRAM interface, it should only do a 4-word burst.  The EMIF SBSRAM interface also assumes that the SBSRAM supports internal advance counter.  

    The DSP will begin by generating only the starting address.  Then, the EMIF address lines will not change because it will assume that the SBSRAM will internally auto increment the address at each EMIF clock.  After 4-word burst, the EMIF will strobe out the next starting address.

    --Christina

  • 0 in reply to clam
    Prodigy 240 points

    Thanks. I think we have my customer on the right path now. But she has another question. You menitoned the SBSRAM interface should only do a 4-word burst. They need to do a 3-word burst for their application. Is this possible?

    Thanks!

    Dan

  • 0 in reply to DanR
    TI__Expert 8785 points

    I don't think there is a way to configure the burst size, so it should only support 4-word bursts. 

    --Christina