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66AK2H14: DDR3 Minimum Write Leveling Skew limit

Madhu Sharma
Expert 2915 points

Part Number: 66AK2H14

Hi,

I am using 66AK2H14 keystone II device in one of our designs.

In DDR3 Design Requirements for KeyStone Devices Application Report, it is mentioned that the write-leveling process in the DDR3 interface imposes a limit on the maximum and

minimum skew between the command delay and the data delay. Please clarify below mentioned points related to that: 

1) Whether this is applicable to Keystone II devices also?

2) In my board, maximum write leveling skew limit is met but minimum skew requirement is not met. Even in the K2H EVB, it looks like the minimum skew requirement is not met ( for example, 

SOC_DDR3B_EDQ48 net has length 1062.05 mils but the address line for that DDR IC has length of about 2425 mils. So the difference is 1363 mils. 
But table 18 of the document mentions that this must be at least 1805 mils.) So whether this will cause any functionality issues?

Thanks & Regards,
madhu

  • 0
    TI__Guru**** 161600 points
    Hi,

    1). The DDR3 Design Requirements for KeyStone Devices Application Report is a common document for both Keystone II and Keystone I devices.

    2). You should follow the design guide. Regarding:
    Even in the K2H EVB, it looks like the minimum skew requirement is not met ( for example, SOC_DDR3B_EDQ48 net has length 1062.05 mils but the address line for that DDR IC has length of about 2425 mils. So the difference is 1363 mils. But table 18 of the document mentions that this must be at least 1805 mils.) So whether this will cause any functionality issues?


    If you're certain that your DDR layout is the same as the K2H EVM, than you should be fine.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Expert 2915 points

    Hello Yordan,

    Thanks for the reply.

    Based on the document, main factor impacting the minimum limit is tWLS ( write-leveling setup time from rising CK, CK# crossing to rising DQS, DQS# crossing)

    So I would like to know is there any way to delay the DQS, DQS# outputs compared to CK, CK#.

    If there is a delay by default, Please let me know its value.

    Thanks & Regards,

    Madhu

  • 0 in reply to Madhu Sharma
    Expert 2915 points

    Hello,

    Could someone please reply to above query?

    Thanks & Regards,

    Madhu

  • 0 in reply to Madhu Sharma
    TI__Mastermind 46460 points

    Madhu,

    The document headings clarify that those min and max routing skew limits are only applicable to KeyStone-I devices.  66AK2H is a KeyStone-II device and these limits do not apply.  The dynamic delay calculation removes this limitation.

    Tom