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AM3352: Cache invalidate procedure

Alex Medina
Intellectual 340 points

Part Number: AM3352

Hi!

I want to use the AM355x processor as “bare metal” for my application. I enable the MMU and Caches.

I have the problem with cached buffers, when data transfers by DMA. Sometimes (about one error per two hours) I get wrong data (aligned on the cache boundary, total size of buffer is more than 1 KB) from peripheral if I read it using the DMA.

Suggest me, please, where can I read recommendations about the order of the operations read/write operations using the DMA and cache. My order:

1. Tx data: Write to buffer; Clean buffer; DSB(or DMB?); Write data from buffer by DMA.

2. Rx data: Read data to buffer by DMA; Invalidate buffer; DSB(or DMB?); Read data.

 

Thanks!

  • 0
    TI__Guru**** 393215 points
    The factory team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 90565 points
    Alex, how are you setting up the MMU for the regions of memory you are using for the buffer? What are the memory attributes for these regions? If you don't want to go thru and clean or invalidate everytime you access the buffer, you could setup the region as non-cacheable, but that may affect your performance.
    I think in general your order of operations is correct. If the ARM core writes to the buffer, you have to perform a clean before the DMA accesses it, and conversely, if the ARM core reads from the buffer, you have to invalidate the cache before the read.
    Are you ensuring that the DMA operations and the cache maintenance operations are not overlapping? This may cause the infrequent issues you are seeing.

    Regards,
    James
  • 0 in reply to JJD
    Intellectual 340 points 
    Hi James!
My thunks!

    My problem had disappeared after the following steps:

    1.Aligned all buffers on cachline bound. 
    2.Aligned the size of the buffers on cachline bound. 
    3.Clean the buffers before EDMA.
    4.Invalidate the buffers before EDMA. 

    Regard Alex.