AM4372: RMII issue, schematic review needed

Dimitrius

Part Number: AM4372

Hello All,

My customer is going to use AM4372 with 2 ethernets (RMII). They have their own board, the board does not work. Unfortunately in the web there are no samples with AM43** and 2 ethernets. It seems to me something missed at customer's board. They think about 50MHz clocking to Sitara...

In attached file you can find PCB schematic. I have PDF with PNs written as text (not picture) and customer's sensitive information, I could send one to your email.

Best regards,

Dmitry

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Dmitry,

You should be aware that schematic reviews cannot be submitted on the E2E. There is an established internal procedure for this.

0 -DK- over 8 years ago

TI__Mastermind 27890 points

I don't see 50MHz to the MACs or the PHYs. Typically this 50MHz clock (REFCLK) is sourced externally via an oscillator and shared by the MAC and PHY.

0 Konstantin Rodnov19 over 8 years ago in reply to -DK-

Prodigy 30 points

If I add a resistor 47R between pin A16 CPU (RMII1_REFCLK) and pin 3 of oscillator Y500 this will be enough (for first channel) ? Please pay attention to the resistor R521, through which the clock is fed to PHY. It is enough?

0 -DK- over 8 years ago in reply to Konstantin Rodnov19

TI__Mastermind 27890 points

Hello,

This would be a good start, but keep in mind that RMII timing is very tight so you may run into timing issues by unbalancing the RMII REF_CLK lengths in the process of adding this wire. Further work would be to ensure that your pinmuxing is correct for RMII1 and that the Port1 MAC is properly configured for REF_CLK input mode.

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AM4372: RMII issue, schematic review needed