Part Number: DRA756
We did the power estimation of DRA756 processor using TI provided "Vayu_Power_Spreadsheet_v1p5.xlsm" and "VayuResourceLoading_v1p2.xlsx".
For "VDD_CORE" we got around 2.17 A. As per the EVM design / PMIC datasheet, VDD_CORE is powered by SMPS 9 of PMIC which is rated for 2A max.
We are seeing a violation here as SMPS 9 may not be sufficient for providing VDD_CORE requirement.
Our design is very similar to EVM design and we use both EMIF (EMIF1 512Mx16 with ECC, EMIF2 512Mx16).
I understand the VDD_CORE is related to EMIF.
I would like to know if there is anything else the VDD_CORE is catering to? Also what is the max current estimated for VDD_CORE in the EVM design?
Or Is there anything i would have done wrong in the power estimation?
