• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 98 subscribers
  • Views 1132 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2G12: Interconnect from ARM/DSP to GPMC

Hiroyasu Tazawa1
Guru 12350 points
Part Number: 66AK2G12


Hi,

Let me talk about interconnect of 66AK2Gx.

My customer want to access from ARM/DSP to GPMC.
It means ARM/DSP set register set.

I see Figure 3-2. TeraNet_DMA Master-Slave Connections.
I understand DSP access the GPMC through the Red line and
ARM access the GPMC through the Blue line

This understanding is correct ??

Best Regards
Hiroyasu

  • 0
    TI__Guru**** 161600 points
    Hi,

    There is no direct connection between C66x CorePack or ARM CorePack and GPMC.
    However GPMC is directly connected to MSMC_0_SYS_MST port via TeraNet. See Table 3-3. TeraNet_DMA Connectivity Matrix.

    So, yes, your understanding is correct. Both C66x & ARM can access GPMC through MSMC_0_SYS_MST.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 12350 points

    Hi, Yordan

    I'm sorry. It was late.

    Thank you for your reply, I understood but I have an another question.

    Can you tell me way of internal bus between  MSMC_0_SYS_MST port and GPMC.

    Becase my customer want to know about internal bus speed.

    Best Regards

    Hiroyasu

  • 0 in reply to Hiroyasu Tazawa1
    TI__Guru**** 161600 points
    Hi Hiroyasu,

    Not sure what you mean by "way of internal bus between MSMC_0_SYS_MST port and GPMC", but as explained in Section 3.1.1 System Interconnect Overview:
    "All modules and subsystems in the device communicate with each other through the system interconnect. It is partitioned into three sections: main data (TeraNet_DMA), main configuration (TeraNet_CFG) and always on (TeraNet_AON) interconnect. Each of these three sections is composed by several TeraNets, which are non-blocking switch fabrics enabling fast and contention-free internal data movement. They also provide low-latency and concurrent data transfers between master and slave peripherals"

    Also Table 3-3. TeraNet_DMA Connectivity Matrix shows that there is a direct connection between MSMC_0_SYS_MST port and GPMC. There is also an MPU (memory protection unit), which you can configure if you want or if your application requires it. The internal switches in TeraNet are pre-configured to establish the path, you cannot control them by sw.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 12350 points
    Hi, Yordan

    O.K. I understood it has direct connection between MSMC_0_SYS_MST port and GPMC.
    So My customer want to know about internal bus clock between MSMC_0_SYS_MST port and GPMC.
    Is it possible to answer this question?

    Best Regards
    Hiroyasu
  • 0 in reply to Hiroyasu Tazawa1
    TI__Guru**** 161600 points
    Refer to Figure 3-2. TeraNet_DMA Master-Slave Connections & Table 3-2. System Interconnect Clocks and Resets:
    The path between MSMC_0_SYS_MST & GPMC goes through:
    MSMC -> TeraNet_M_1_256_2 -> Br_msmc_sys1 -> TeraNet_M_3_128_0 -> MPU_3 -> Br_MP_9 -> TeraNet_P_3_32_11 -> GPMC

    So TeraNet path is TeraNet_M_1_256_2, TeraNet_M_3_128_0 & TeraNet_P_3_32_11. According to Table 3-2:
    TeraNet_M_1_256_2 clock frequency is equal to CHIP_CLK1
    TeraNet_M_3_128_0 clock frequency is equal to CHIP_CLK1/3
    TeraNet_P_3_32_11 clock frequency is equal to CHIP_CLK1

    CHIP_CLK1 clock frequency is 600 MHz or 1GHz, as per Table 5-1. Supported Max Frequency of 66AK2G12 Datasheet.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 12350 points
    Hi, Yordan

    Thank you for your kindly support !
    I got it.

    Best Regards
    Hiroyasu