Hi Support,
my customer is facing an issue with AM5728 SPI, partially fixed in the past.
They are reporting me the following:
one of side topics was SW issues regarding AM57xx CPU, where our experience had been required, with both already solved and still open issues.
I'm sending you a brief summary of what we have presented here.
In short: a) RTOS bug in SPI driver has been quick-fixed by Brno - no longer an issue, just FYI.
b) An ancient CSL SPI code example for c66x core has been found in TI's PDK codebase ... It is still desirable that TI fixes this issue, so that we can re-use it for our purpose
c) (an extension of b)) It is also desirable that TI extends the CSL SPI code example for c66x code so that it demonstrates the use of DMA crossbar for SPI4.
d) There is also an issue with Ethernet driver dropping packets without user notification when sending a UDP packet stream; However, this has not so critical priority, since we have already developed a workaround. I'm also not sending any details now about this.
I've also attached some supporting documentation. If you need more, please don't hesitate to ask.
Just a small clarification: The part, that we have corrected, was in a driver that is called from TI-RTOS based project, i.e. there are thread-synchronization primitives, there are soft-IRQs and other RTOS-bound components.
Now, we need a more bare-metal-like example, which doesn't rely on any of those TI-RTOS components, so that we will have everything under direct control. Moreover, we need it to work not only for ARM but also for DSP, which is our target core. We have found such an example under CSL (Chip Support Library, which is also part of Processor SDK) - this is the example we are talking about in the documents, I've sent you. However, this example doesn't build for DSP currently, because of some ancient API calls that are used in it and which are no longer supported by the rest of the package - apparently, this part of the example has been left unmaintained for a long time. And this is, what I was talking in the b) point of the last email.
To be more exact, if you find a source file in $PDK_INSTALL/ti/csl/example/mcspi/mcspiMasterSlave/mcspiMasterSlave_spi1_spi2.c, and find a function definition of EDMA3IntConfigure, you may take a look on just a few starting lines of code:
/*
** This function configures the AINTC to receive EDMA3 interrupts.
*/
static void EDMA3IntConfigure(void)
{
#ifdef _TMS320C6X
/* Initialize DSP interrupt controller and enable interrupts */
IntDSPINTCInit();
IntGlobalEnable();
/* Map EDMA events to DSP interrupts */
IntRegister(4, Edma3ComplHandlerIsr);
IntEventMap(4, SYS_INT_EDMACOMPINT);
IntEnable(4);
IntRegister(5, Edma3ErrorHandlerIsr);
IntEventMap(5, SYS_INT_EDMAERRINT);
IntEnable(5);
#else
... now, try to find definitions of any of those functions under _TMS320C6X conditionally-compiled block, e.g. IntCSPINTCInit(), IntGlobalEnable(). Anywhere in the rest of Processor SDK, you won't find anything. They are simply gone probably with some previous SDK version update.
We, the DSP programmers, are intended to use a suitable replacement of those obsolete API calls. This is, what we would be happy to get from TI now - an up-dated example that works also for c66x core.
Moreover, we would be glad to see an extension of this example, that will also demonstrate, how to configure DMA crossbar, so that we could use also SPI4 (in this example, only SPI1,2 are used, which don't need to rely on DMA crossbar)
Please also see attached PDF for reference.
Thanks and regards,
Alberto
