AM3352: DDR SI analysis questions

Is there any information?

Hi Brad-san,

I have one new question.

I read the following sentences and thought that signal integrity analysis was necessary when using DDR3 point-to-point topology.

However, according to the routing rules, Jedec can be satisfied, so signal integrity analysis is not necessary.

Is this recognition correct?

Best regards,

Sasaki

“Signal integrity” analysis relates to the shape of the waveforms, amount of over/undershoot, etc. The IBIS models are suitable for that purpose. Your vix measurement does not fall into that bucket. Once you start looking at relative timing between signals, now you are into timing analysis which is not valid.

Thank you for your reply.

I understood that signal integrity analysis is suitable.

So I will return to the first question of this thread.

When I do SI analysis, which one is the correct way ① and ②?

1. Result of signal integrity analysis with only differential signals of DQS and DQS_N in ZCZ package.
2. Results of signal integrity analysis of the differential signals of DQS and DQS_N and the data buses DQ0 to DQ7 in ZCZ package.

Best regards,

Sasaki

#2 is fine as long as you're looking at each signal in isolation (i.e. not looking at relative timing, etc.).

See the pin mapping here:

http://processors.wiki.ti.com/index.php/How_to_use_the_AM335x_IBIS_Models#Additional_Notes_on_ioctrl_Pin_Mapping

For each line in that table, you have the ability to control the drive strength and slew rate.