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How often (uPP)WAIT signal will be asserted for a data transmission at certain clock rate?

Hi,

I'm planning to use uPP(receive only) to interface to a kind of parallel port, which has no wait function, that means it will send data non-stop until it finishes. With a little external logic it can be done, just the WAIT signal is a bit tricky. If WAIT is asserted by uPP, the result will be data lose. The clock will be 12Mhz, or 24MHz max, so under such clock rate, will uPP asserts WAIT often, not often, or very rare, or not at all? Assume DSP will be doing this data transfer only.

Any one who has experience in using uPP, can you give some hints?

 

Thanks a lot,

clliu