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VPBE/DAC Clocking

Ferhat OLGUN
Expert 1080 points


Hi,

For my 480x272 TFT LCD I want to generate a 9Mhz VCLK using PLL2 mode(sprue14b 5.2.5). In order to do that I want to set

-PLLM of PLL2 to "x10"
-PLLDIV1 to "/15"
-PLLDIV2 to "/1"
-VENC_DIV_2 to "/2"

so that I can modify 27MHz MXI to x10 /15 /2 = 9 MHz. and I also want to set the timing signals for proper sync. signals in logicpd_encoder.c.

But I could not find in which portion of the code these PLL registers are initialized. Could you please help me to change these registers? Is there any documents, application reports and patches which help me to modify the VPBE driver for different resolution LCDs?

Ferhat

  • 0
    TI__Mastermind 37340 points

    PLLs are normally initialized in u-boot.  Please note that PLLs control clocks for ARM, DSP, and a variety of peripherals; during boot-up linux kernel uses ARM clock to calculate important clock parameters for Linux operating system, hence it is a bad idea to miss with certain clocks after bootup.  With regards to PLL2, which is what appears you are trying to change, please note that PLLDIV2 setting on PLL2 also affects DDR2 memory controller.  Bottom line, please consider your entire system when missing with PLL settings; a simpler approach may be to add external VPBE clock.

  • 0 in reply to Juan Gonzales
    Expert 1080 points

    As I understand from SPRUE14B 6.3(Arm Subsystem) PLL2 controls only VPSS and DDR2 PHY. Does it make any problem after boot-up both

    -dividing PLLM by 2

    -multiply PLLDIV2 by 2   so that PLL2_SYSCLK2 for DDR2 PHY does not change?

    This also divides PLL2_SYSCLK1 for VPSS  by 2 and I can divide 540MHz MXI by 60 by changing PLLDIV1 ratio to 15 and setting Venc_div_2. (540/ (2X15X2) =9  )

    If it is not possible I can use the VPBE CLK method as you have mentioned.

    Thanks