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tms320c6748: Rising edge interrupt on GPIO5[8] not working.

AAAA PPPP
Expert 1410 points

Part Number: TMS320C6748
Other Parts Discussed in Thread: TMS320C6748

Hello,

I am using tms320c6748 lcdk kit. I want to configure GPIO5[8] that comes to J14 pin 27 as external interrupt on rising edge. As given in c6748 technical reference manual page 899 I want to do following:

To configure a GPIO interrupt to occur only on rising edges of the GPIO signal:

• Write a logic 1 to the associated bit in SET_RIS_TRIG.

• Write a logic 1 to the associated bit in CLR_FAL_TRIG.

But in my program when I try to program those registers , they are not programmed. Given below is my program. Please help me find mistake.

#include "gpio.h"
#include "psc.h"
#include "interrupt.h"
#include "soc_C6748.h"
#include "lcdkC6748.h"

#include"hw_types.h"

#include"hw_syscfg0_C6748.h"


/****************************************************************************/
/* LOCAL FUNCTION PROTOTYPES */
/****************************************************************************/
static void Delay(volatile unsigned int delay);

/****************************************************************************/
/* GLOBAL VARIABLES */
/****************************************************************************/

/****************************************************************************/
/* LOCAL FUNCTION DEFINITIONS */
/****************************************************************************/

#define gpio_base_add 0x01e26000

int flag=0;
void GPIOBank5Pin6PinMuxSetup();

static void gpioIsr();
static void SetupInt(void);
static void ConfigureIntgpio(void);
int main(void)
{


/* The Local PSC number for GPIO is 3. GPIO belongs to PSC1 module.*/
PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_GPIO, PSC_POWERDOMAIN_ALWAYS_ON,
PSC_MDCTL_NEXT_ENABLE);

/* Pin Multiplexing of pin 8 of GPIO Bank 5.*/
GPIOBank5Pin6PinMuxSetup();

/* Sets the pin 89 (GP6[13]) as output.*/
GPIODirModeSet(SOC_GPIO_0_REGS, 87, GPIO_DIR_INPUT);

SetupInt();

/* Configure AINTC to receive and handle UART interrupts. */
ConfigureIntgpio();

// HWREG(gpio_base_add+0x74)=0x00400000; //set set_ris_trig45
// HWREG(gpio_base_add+0x80)=0x00400000; //set clr_fal_trig45

HWREG(0x01e26074)=0x00400000; //set set_ris_trig45
HWREG(0x01e26080)=0x00400000; //set clr_fal_trig45

while(1);

}

/*
** \brief This function checks the insertion status of the MMC/SD card
** in the device and prints related statements on the serial
** commuincation console of the external device.
**
*/

/*
** \brief This function can be called to generate a delay.
*/

static void Delay(volatile unsigned int delay)
{
while(delay--);
}

void GPIOBank5Pin6PinMuxSetup()
{

HWREG(0x01c14150) |=0x00000080; //set corresponding bits in pinmux12
HWREG(0x01c14150) &=0xFFFFFF80;
}


static void gpioIsr()
{

flag=1;
HWREG(gpio_base_add+0x74)=0x00000000; //set set_ris_trig45
HWREG(gpio_base_add+0x80)=0x00000000; //set clr_fal_trig45

}

static void SetupInt(void)
{
#ifdef _TMS320C6X
// Initialize the DSP INTC
IntDSPINTCInit();

// Enable DSP interrupts globally
IntGlobalEnable();
#else
/* Initialize the ARM Interrupt Controller(AINTC). */
IntAINTCInit();

/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();

/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();

/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
#endif
}

static void ConfigureIntgpio(void)
{
#ifdef _TMS320C6X
IntRegister(C674X_MASK_INT4, gpioIsr);
IntEventMap(C674X_MASK_INT4, SYS_INT_GPIO_B5INT);
IntEnable(C674X_MASK_INT4);
#else
/* Registers the UARTIsr in the Interrupt Vector Table of AINTC. */
IntRegister(SYS_INT_GPIO_B5INT, gpioIsr);

/* Map the channel number 2 of AINTC to UART2 system interrupt. */
IntChannelSet(SYS_INT_GPIO_B5INT, 2);

IntSystemEnable(SYS_INT_GPIO_B5INT);
#endif
}


/*****************************END OF FILE************************************/

Thanks in advance.

With Regards

Shalini

  • 0
    Guru 26430 points
    Your code looks okay for GPIO5[6] or J14 pin 27. Reading the SET_RIS_TRIG and CLR_FAL_TRIG registers will return the currenty interrupt enable. Not the last set or clr values. These lines
    HWREG(gpio_base_add+0x74)=0x00000000; //set set_ris_trig45
    HWREG(gpio_base_add+0x80)=0x00000000; //set clr_fal_trig45
    do nothing at all.
  • 0 in reply to Norman Wong
    Expert 1410 points
    Hello,

    Thanks for reply. But these lines are within ISR. I was able to see that HWREG(0x01e26074)=0x00400000; //set set_ris_trig45
    sets bit 22 in set_ris_trig45 and clr_ris_trig45. Also HWREG(0x01e26080)=0x00400000; //set clr_fal_trig45 do not set any value in clr_fal_trig45. Why do this happen? without it setting how can I set interrupt?

    Please help. Thanks in advance.

    With regards
    Shalini
  • 0 in reply to AAAA PPPP
    Guru 26430 points
    In the TRM
    Table 19-13. GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) Field Descriptions

    Disable falling edge interrupt detection on GPk[j]. Reading the GPkPj bit in either SET_FAL_TRIGn or
    CLR_FAL_TRIGn always returns an indication of whether the falling edge interrupt generation function
    is enabled for GPk[j]. Therefore, this bit will be one in both registers if the function is enabled, and zero
    in both registers if the function is disabled.

    Thats means setting a bit 22 in clr_fal_trig45 will result in the interrupt being disabled. Reading back from clr_fal_trig45 will show the current interupt enable (cleared)NOT the value you just wrote.
  • 0 in reply to Norman Wong
    Expert 1410 points
    Hello,

    Thanks for reply. Regretting delay in response. I was not at work few days.

    I want to disable interrupt at falling edge. So I want to set clr_fal_trig45 at pin 22. I am setting HWREG(0x01e26080)=0x00400000; //set clr_fal_trig45 ie bit 22 in register to high. But when I read back I see a zero only. How can the interrupt I enabled be disabled automatically ,when I have not given any statement.

    Thanks in advance

    With Regards
    Shalini
  • 0 in reply to AAAA PPPP
    Guru 26430 points
    Not quite sure where the misunderstanding is occurring. What you are describing is exactly what the manual says will happen. This line

    HWREG(0x01e26080)=0x00400000; //set clr_fal_trig45 ie bit 22 in register to high

    will clear the falling edge interrupt function for each value of 1. A value of 0 will not change anything. So for 0x00400000, that means that bit 22 in the falling edge interrupt function is cleared. Effectively writing a 1 to the clear register will cause a write 0 to the interrupt function register behind it.

    Let say you read back from the set and clear registers into two temp variables:

    x = HWREG(0x01e2607c); //read set_fal_trig45 to access falling edge interrupt function register
    y = HWREG(0x01e26080); //read clr_fal_trig45 to access falling edge interrupt function register

    Both x and y will show the value of bit 22 to be cleared or 0 or that the falling edge interrupt function is disabled. It does not show the value you last wrote to the clear or set register.

    Similarly, writing a 0 to the set register will not clear the interrupt enable register. You have to write a 1 to the clr register. Writing 0s to set or clear registers have no effect. You cannot directly write to the interrupt function register but indirectly act via the clr and set registers.