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Linux/DRA745: Linux on CPU0 and bare-metal or Android on CPU1

lal bosco lawrence
Intellectual 370 points
Part Number: DRA745

Tool/software: Linux

Hi,

I am able to switch off CPU1 and boot the linux on CPU0 (DRA74x-J6).  Now  I want to run the bare-metel or Android OS on CPU1 using AMP.

Please guide us to do this ..

Thanks,

Lal Bosco

  • 0
    TI__Mastermind 19030 points
    Hi Lal Bosco,
    Cortex-A15 MPU is a dual-core SMP (Symmetric MultiProcessing) MPU, i.e. CPU0 and CPU1 are not independent CPUs.
    You can still run different OS/applications on Cortex-A15 (MPU) , Cortex-M4 (IPU), or C66x (DSP) depending on OS availability.

    Regards,
    Stan
  • 0 in reply to Stanislav Stilyanov
    Intellectual 370 points
    Hi Stan,

    Thanks for the reply.

    1. We have a basic doubt, can we configured DRA7XX to support AMP mode so that it uses only one core (Core 0) to boot Linux and the Core 1 running bare metal?
    2. how can we do this once the core 1 comes out of reset?

    Thanks,
    Lal Bosco.
  • 0 in reply to lal bosco lawrence
    TI__Mastermind 19030 points
    Hi,
    1. I think configuring Cortex A15 to AMP is not specific to DRA7xx, it is more closely related to ARM Cortex architecture. I would suggest you to check ARM community forums for this.
    2. Core 0 (i.e. any software running on it) is responsible of booting Core 1. That includes:
    - loading software image for Core1 to RAM
    - Supplying Core 1 with image start address
    - Release Core 1 from WFE state
    See more details in DRA75x/DRA74x TRM, Section 32.3.4.1 Startup

    Regards,
    Stan
  • 0 in reply to Stanislav Stilyanov
    Intellectual 370 points
    Thanks for the information which is really helping us.

    How do we get the CPU1 out of reset ?

    Thanks,
    Lal Bosco L
  • 0 in reply to lal bosco lawrence
    TI__Mastermind 19030 points

    Hi,

    CPU1 is released from reset automatically by PRCM or by ROM code (I don't know who exactly but it doesn't really matter). After that, CPU1 is held in wait-for-event (WFE) which is similar to reset state because CPU1 is not executing anything. After ROM hands over to bootloader, bootloader can wake up the slave CPU by executing a SEV command.

    Two internal memory-mapped registers are available to the OS for communicating start-up information.
    The AUX_CORE_BOOT_0 and AUX_CORE_BOOT_1 registers are in the MPU WakeupGen domain.
    • AUX_CORE_BOOT_0 is used as a status register to signal the slave CPU that it must wake up after
    the send event operation initiated by the master CPU.
    • AUX_CORE_BOOT_1 contains the physical address location to which the slave CPU must jump after
    wakeup.
    See the memory mapping of these registers in Section 4.4.10, MPU_WUGEN Registers in Dual Cortex-
    A15 MPU Subsystem.

  • 0 in reply to Stanislav Stilyanov
    Intellectual 370 points
    Thanks for the information that is helping us to move forward.
    We are reading the TRM and tracing the code.
    Will update once we move forward.

    Thanks,
    Lal Bosco.