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AM3352: DQS slew rate

z z24
Prodigy 30 points

Part Number: AM3352

Hello:

We do the DDR SI test by Agilent Oscilliscope.

Test results show that SRQdiffR and SRQdiffF are failed.

According to JEDEC definition, the value should between 5 to 10V/ns. Ours result is a little bit than 5V/ns.

After check user manual of AM335x, there are some registers can adjust slew rate of DQS: 

1404h ddr_cmd0_ioctrl Section 9.3.1.87
1408h ddr_cmd1_ioctrl Section 9.3.1.88
140Ch ddr_cmd2_ioctrl Section 9.3.1.89
1440h ddr_data0_ioctrl Section 9.3.1.90
1444h ddr_data1_ioctrl Section 9.3.1.91

(according to the datasheet, I use the same value for all these registers, I change slew rate only, and also both slew rate and output impedance. Default value in our FW is 0x183, I change to 0x83, then 0xE3)

but after change register value to highest, no changes in the waveform.

Could you help to check, if we want to change slew rate of DQS, by modifying of registers above is enough or not?

Thanks

  • 0
    TI__Guru**** 393215 points
    The DDR experts have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Genius 9655 points
    Hi,

    Apologize for the delay in our response due to holiday time.

    - SRQdiff (rise) and SRQdiff (fall) are defined by JEDEC for DRAM.
    - Not sure why you are measuring these values - did you notice any memory read/write failures?
    - We are not able to adjust the DRAM slew rate since this is a DRAM parameter and not AM335x related.
    - The impedance/slew rate of AM335x will impact the DQ, DQS rise/fall when AM335 is driving the data bus and not when DRAM is driving the data bus

    I did not see the memory type specified, but assuming it is DDR3L, even though JEDEC has a requirement of 5V/ns - 10V/ns, some memory manufacturers have better specs than JEDEC. Therefore, I'd also recommend to verify this parameter with the actual DRAM part capability in addition to JEDEC compliance.

    Let us know if you have any other questions.

    Regards, Siva
  • 0 in reply to sivak
    Prodigy 30 points

    Hello, Siva

    thanks for your reply.

    Testing these parameters are used to check our design, make sure t that our HW design does not contain any potential issues with SI. And all these tests are checked by Agilent oscilloscope with a dedicated DDR3 test application. it is not measured manually.

    SRQdiff (rise) and SRQdiff (fall), according to JEDEC, it is defined to check DQS slew rate, the method is check rising/falling edge changed from -300mV to 300mV within a specified time. Now our issue is slow rate too slow.

    Since DQS is only issued by AM335x only, so I think to modify registers of DDR PHY can let DQS slew rate meet JEDEC spec.

    But actually, after changing slew rate to Fastest (Default is Slow), no changes in DQS slew rate.

    for the DDR: we are using DDR3L, MPN is MT41K256M16TW-107:P from Micron. But we are using it as DDR3.

    And DDR date rate is set to 800, but this part can support 1866.

    Could you help to check to change slew rate, how many registers should be changed simultaneously?

    thanks.

  • 0 in reply to z z24
    TI__Genius 9655 points
    As noted in my previous reply, the SRQDiff(rise) and SRQDiff(fall) parameters are defined for the DDR3 DRAM device. These are characteristics of the DDR memory device output driver with the AC load as defined in the JEDEC spec. Therefore, these are applicable when DRAM device is driving the memory bus i.e. DQS/DQS#. I'm actually unclear on your motivation to measure this parameter since this is purely a DRAM characteristic and there is nothing much you can do here. Please review the JEDEC standard JESD79-3F Section 9.4 and Section 9.5 which describes the AC load for slew rate measurements.

    AM335x slew rate control impacts slew rate of the AM335x output drivers i.e. when AM335x is driving the data bus. DRAM data bus is a bidirectional bus and driven by AM335x only during a WRITE operation.

    Please let us know if you need any further help on this.