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C64x+ cache

Len Koss
Intellectual 300 points
Other Parts Discussed in Thread: OMAP3530

 

Hello,

I'm currently using the OMAP3530 with CCS version 4.2.1 and DSP/BIOS 5.41.04.18.  I'm running an algorithm on the resident C64x+ core and I'm encountering a puzzling problem involving the L1D and L1P cache memory.  I have all data structures in internal memory split between L1DSRAM and IRAM and the code is in DDR.  However, when I move the code into IRAM the algorithm performance in terms of cycles needed to complete, gets noticeably worse.  Why would I take a performance hit by moving the code inside?  I would've thought I'd get improved performance.

 

Thanks,

Len 

  • 0
    TI__Mastermind 32475 points

    Len,

    What you stated doesn't quite make sense so what could be happening depends on what your cache configurations are for L1D, L1P, and L2 (IRAM).  I assume you probably have L1P as 32KB cache? Otherwise code being in DDR would be really slow.  How much of your IRAM is cache versus RAM?  How much of your L1D is cache versus RAM?  You do understand that acesses to IRAM is 2x as slower than L1D acesses right?  Without knowing what your memory map looks like, Its hard trying to explain what's going on here.

    For more information on c64x+ cache see: http://focus.ti.com/lit/ug/spru862b/spru862b.pdf

    Judah