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RTOS/AM5728: Vector number in PCIe example

Manjula KS
Intellectual 430 points
Part Number: AM5728
Other Parts Discussed in Thread: TMS320C6678

Tool/software: TI-RTOS

Hi,

In the PCIE example code, in PlatformSetupMSIandINTX function 

cpuEvent = 48;
xbarIndex = cpuEvent - 31;
vector = 12;

/* Configure xbar */
CSL_xbarIrqConfigure (cpu, xbarIndex, CSL_XBAR_PCIe_SS1_IRQ_INT1);

/* Construct Hwi object for this UART peripheral. */
HwiP_Params_init (&hwiInputParams);
hwiInputParams.name = "PCIE_MSI_AND_INTX";
hwiInputParams.arg = (uintptr_t)handle;
#if defined (_TMS320C6X) || defined (__ARM_ARCH_7A__)
hwiInputParams.priority = 0;
#else /* M4 */
hwiInputParams.priority = 0x20;
#endif
hwiInputParams.evtId = cpuEvent;
pcieHwi = HwiP_create(vector, PlatformMsiIntxIsr, &hwiInputParams);

How are the values for vector, cpuevent and xbarIndex choosen.  

Here mapping PCIESS1 crossbar to IRQcrossbar of DSP1 enables interrupting the DSP1 of PCIESS1. so xbarIndex is choosen randomly or any perticular reason behind?? What is the vector 12.

Please clarify on this.  What are we doing in this piece of code

Thanks & Regards

Manjula

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points
    Hi,

    You can look at Table 17-3. DSP1_INTC Default Interrupt Mapping of AM572x TRM.

    DSP1_IRQ_48 17 CTRL_CORE_DSP1_IRQ_48_49[8:0] 17 Reserved Reserved by default but can be remapped to a valid interrupt source

    irq_48 is reserved, since this is a standalone test program, this can be used.

    Vector: 12, you can select any vector between 4 and 15 (inclusive). TRM 17.1: There are two Digital Signal Processing (DSP) subsystems in the device - DSP1, and DSP2. Each DSP subsystem integrates an interrupt controller - DSPx_INTC, which interfaces the system events to the C66x core interrupt and exceptions inputs. It combines up to 128 interrupts into 12 prioritized interrupts presented to the C66x CPU.

    This is C66x, you can look at See: processors.wiki.ti.com/.../Configuring_Interrupts_on_Keystone_Devices or TMS320C6678 datasheet section 7.10.1: The CPU interrupts on the C6678 device are configured through the C66x CorePac Interrupt Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic.

    Regards, Eric