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Linux/DRA725: the M4 of dra725 operation DCAN module

Part Number: DRA725

Tool/software: Linux

Hi, 

do the M4 of dra725 support  DCAN module?

i want to use the CAN module on the M4, but i don't find related information;

Regards,

Cesar

  • Hi Cesar,

    DRA7xx series have flexible IRQ routing through an IRQ crossbar. I think it is possible to map DCAN IRQs on IPU and run software.driver on it.

    regards,

    Stan

  • Hi Stan,

    do you have a app example about DCAN run on the IPU,
    how i operate thd sdk about IPU module.

    thanks,
    Cesar

  • Hi Cesar,

    PDK has CSL DCAN loopback example (csl_dcan_loopback_app) that can be run on IPU.
    In order to build this example from Vision SDK please refer to: processors.wiki.ti.com/.../PDK_FAQ

    Regards,
    Rishabh
  • Hi Rishabh,

    i find the example processors.wiki.ti.com/.../PDK_TDA_CSL_User_Guide
    but i don't find the PDK source code download.

    Regards,
    Cesar
  • Hi Cesar,

    You can load the Vision SDK code from www.ti.com/.../PROCESSOR-SDK-TDAX.
    PDK is driver component for Vision SDK.

    Regards,
    Rishabh
  • Hi Rishabh,

    thank you for your help,

    i read the ipu example,but how the print  to terminal

    Regards,

    Cesar

  • Hi Cesar,

    You can use Vps_printf when you are using Vision SDK.
    Just grep/search the Vision SDK code to see how it is used/implemented.

    Regards,
    Rishabh
  • Hi Rishabh,

    i want to print IPU(M4) debug Info, output which uart,how to do?

    Regards,
    Cesar
  • Hi Cesar,

    In case you are looking for simple prints you can use UART console utility. This utility is present in <vsdk>\ti_components\drivers\<pdk>\packages\ti\csl\example\utils\uart_console.
    You need to connect UART terminal at 115200 baud rate, 8 bit data, parity none and stop bit 1.
    You should use UART1 for DRA72x/TDA2Ex EVM.

    Regards,
    Rishabh
  • Hi Rishabh,

    I have one more question.

    i find the ipu gpio example, the path:

    $(toolchain)/sysroots/armv7ahf-neon-linux-gnueabi/usr/share/ti/ti-pdk-tree/packages/ti/csl/example/gpio/gpio_toggle/

    the gpio example set gpio1_14, the file:

    /*
     *  Copyright (C) 2013-2016 Texas Instruments Incorporated - http://www.ti.com/
     *
     *  Redistribution and use in source and binary forms, with or without
     *  modification, are permitted provided that the following conditions
     *  are met:
     *
     *    Redistributions of source code must retain the above copyright
     *    notice, this list of conditions and the following disclaimer.
     *
     *    Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the
     *    distribution.
     *
     *    Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
     *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
     *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     *
     */
     /**
     *  \file   main.c
     *
     *  \brief This file demonstrates toggling gpio pins high and low
     *         using GPIO dal API's.
     *
     */
    
    /* ========================================================================== */
    /*                             Include Files                                  */
    /* ========================================================================== */
    #include "stdint.h"
    #include <ti/csl/csl_gpio.h>
    #if defined (SOC_AM572x) || defined (SOC_AM571x)
    #include <ti/board/board.h>
    #endif
    #include <ti/csl/example/utils/uart_console/inc/uartConfig.h>
    #include <ti/csl/soc.h>
    #include <ti/csl/hw_types.h>
    
    /* ========================================================================== */
    /*                                 Macros                                     */
    /* ========================================================================== */
    /* None */
    
    /* ========================================================================== */
    /*                            Global Variables                                */
    /* ========================================================================== */
    uint32_t pinDirection = GPIO_DIR_OUTPUT;
    
    /*To use UARTConfigPuts(uartBaseAddr, function for prints*/
    /*To use UARTConfigPuts function for prints*/
    #if (defined (SOC_AM572x)) || (defined (SOC_AM571x))
    uint32_t uartBaseAddr = CSL_MPU_UART3_REGS;
    #endif
    #if defined (SOC_TDA2EX) || defined (SOC_TDA2XX) || defined (SOC_DRA75X)
    uint32_t uartBaseAddr = SOC_UART1_BASE;
    #endif
    #if defined (SOC_TDA3XX) || defined (SOC_DRA78X)
    uint32_t uartBaseAddr = SOC_UART3_BASE;
    #endif
    
    #if (defined (SOC_AM572x)) || (defined (SOC_AM571x))
    uint32_t gpio_base_address = CSL_MPU_GPIO7_REGS;
    uint32_t gpio_pin          = 8;
    #elif defined (SOC_TDA2EX) || defined (SOC_TDA2XX) || defined (SOC_DRA75X)
    uint32_t gpio_base_address = SOC_GPIO1_BASE;
    uint32_t gpio_pin          = 14;
    #elif defined (SOC_TDA3XX) || defined (SOC_DRA78X)
    uint32_t gpio_base_address = SOC_GPIO4_BASE;
    uint32_t gpio_pin          = 9;
    #endif
    
    /* ========================================================================== */
    /*                          Function Definitions                              */
    /* ========================================================================== */
    void padconfig_PrcmEnable()
    {
    #if defined (SOC_AM572x) || defined (SOC_AM571x)
        /*Pad configurations */
        Board_initCfg boardCfg;
        boardCfg = BOARD_INIT_UNLOCK_MMR | BOARD_INIT_UART_STDIO | 
                   BOARD_INIT_MODULE_CLOCK | BOARD_INIT_PINMUX_CONFIG;
        Board_init(boardCfg);  
    
        HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_DCAN1_TX,0x0006000E);
        /*Enable GPIO clock*/
        HW_WR_REG32(CSL_MPU_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO2_CLKCTRL_REG,0x102);
         while ((HW_RD_REG32(CSL_MPU_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO2_CLKCTRL_REG) & (0x00030000U)) != 0x0)
            {
                ;
            }
        HW_WR_REG32(CSL_MPU_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO3_CLKCTRL_REG,0x102);
         while ((HW_RD_REG32(CSL_MPU_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO3_CLKCTRL_REG) & (0x00030000U)) != 0x0)
            {
                ;
            }
        HW_WR_REG32(CSL_MPU_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO4_CLKCTRL_REG,0x102);
        while ((HW_RD_REG32(CSL_MPU_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO4_CLKCTRL_REG) & (0x00030000U)) != 0x0)
            {
                ;
            }
    #endif
    #if defined (SOC_TDA2XX) || defined (SOC_TDA2EX) || defined (SOC_DRA75X)
        /*Pad configurations */
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_UART1_RXD,0x00040000);
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_UART1_TXD,0x00040000);
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_DCAN1_TX,0x0006000E);
        /*Enable GPIO clock*/
        HW_WR_REG32(SOC_L4PER_CM_CORE_BASE+CM_L4PER_GPIO2_CLKCTRL,0x102);
        while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE+CM_L4PER_GPIO2_CLKCTRL) & (0x00030000U)) != 0x0)
            {
                ;
            }
        HW_WR_REG32(SOC_L4PER_CM_CORE_BASE+CM_L4PER_GPIO3_CLKCTRL,0x102);
         while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE+CM_L4PER_GPIO3_CLKCTRL) & (0x00030000U)) != 0x0)
            {
                ;
            }
        HW_WR_REG32(SOC_L4PER_CM_CORE_BASE+CM_L4PER_GPIO4_CLKCTRL,0x102);
        while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE+CM_L4PER_GPIO4_CLKCTRL) & (0x00030000U)) != 0x0)
            {
                ;
            }
        /* Set the UART Parameters */
        UARTConfigInit(uartBaseAddr, BAUD_RATE_115200, UART_WORD_LENGTH_8, UART_STOP_BIT_1, UART_NO_PARITY,
                       UART_16x_MODE);
    #endif
    #if defined (SOC_TDA3XX) || defined (SOC_DRA78X)
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI1_SCLK,0x00040001);
        HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI1_CS0,0x00000001);
        /* Set the access to the GPMC registers - Enable GPMC Clock */
        HW_WR_REG32(SOC_L4PER_CM_CORE_BASE + CM_L4PER_GPIO2_CLKCTRL, 0x102);
        while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE +
                        CM_L4PER_GPIO2_CLKCTRL) & (0x00030000U)) != 0x0)
           {
                ;
           }
       HW_WR_REG32(SOC_L4PER_CM_CORE_BASE + CM_L4PER_GPIO3_CLKCTRL, 0x102);
       while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE +
                        CM_L4PER_GPIO2_CLKCTRL) & (0x00030000U)) != 0x0)
           {
                ;
           }
       HW_WR_REG32(SOC_L4PER_CM_CORE_BASE + CM_L4PER_GPIO4_CLKCTRL, 0x102);
       while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE +
                        CM_L4PER_GPIO2_CLKCTRL) & (0x00030000U)) != 0x0)
           {
                ;
           }
        /* Set the UART Parameters */
        UARTConfigInit(uartBaseAddr, BAUD_RATE_115200, UART_WORD_LENGTH_8, UART_STOP_BIT_1, UART_NO_PARITY,
                       UART_16x_MODE);
    #endif
    }
    void delay(void)
    {
        volatile uint32_t i;
        for (i = 0; i < 4000000; i++)
        {}
    }
    
    int main(void)
    {
        volatile uint32_t checkOutput = 1;
    
        padconfig_PrcmEnable();
        
        UARTConfigPuts(uartBaseAddr,"\nGPIO Output App", -1);
        UARTConfigPuts(uartBaseAddr,"\nGenerating a square wave on GPIO pin", -1);
    #if defined (SOC_AM572x) || defined (SOC_TDA2XX) || defined (SOC_DRA75X) || defined (SOC_AM571x) || defined (SOC_TDA2EX)
        UARTConfigPuts(uartBaseAddr,"\nProbe the GPIO1 pin 14 on JP2 connector - pin 1 on EVM", -1);
    #elif defined (SOC_TDA3XX) || defined (SOC_DRA78X)
        UARTConfigPuts(uartBaseAddr,"\nProbe the GPIO4 pin 9 on J6108 connector - pin 1 on EVM", -1);
    #endif
    
        GPIOModuleReset(gpio_base_address);
    
        GPIOModuleEnable(gpio_base_address);
    
        GPIODirModeSet(gpio_base_address, gpio_pin, pinDirection);
    
        while (checkOutput)
        {
            GPIOPinWrite(gpio_base_address, gpio_pin, GPIO_PIN_HIGH);
            delay();
    
            GPIOPinWrite(gpio_base_address, gpio_pin, GPIO_PIN_LOW);
            delay();
        }
    
        return 0;
    }
    /********************************* End of file ******************************/
    
    

    i make it and generate the csl_gpio_toggle_app_ipu1_0_release.xem4

    i copy it to $rootfs/lib/firmware and ln -s csl_gpio_toggle_app_ipu1_0_release.xem4  dra7-ipu1-fw.xem4

    run the system and execute:

    # cd /sys/bus/platform/drivers/omap-rproc/
    # echo 58820000.ipu > unbind
    # echo 58820000.ipu > bind

    the phenomenon:

    I don't know if he works normally, and the gpio pin no change found.

    Regards,

    Cesar

  • Hi Cesar,

    You can run this application via CCS loading.
    I am not aware of how to run it via linux/rootfs.

    Regards,
    Rishabh
  • Hi Rishabh,

    i run the gpio example: csl_gpio_toggle_app_ipu1_0_release.xem4

    but uart1 does  not print info,and change uart part to uart2 also does not print info;

    i don't know the IPU1 if running.

    how to do test。

    Regards,

    Cesar.

  • Hi Cesar,

    You are trying to run the example application through linux.
    Can you run it via CCS.
    There is lot of content available on internet on how to use CCS.
    www.youtube.com/watch

    Regards,
    Rishabh
  • Hi Rishabh,

    i can't open the URL;
    can you offer ccs ipu all config and so on.

    Regards,
    Cesar
  • Hi Cesar,

    Vision SDK has docs\TrainingSlides folder which contains different training slides.
    CCS_Debug_Trace.pdf document contains steps on how to run VSDK application using CCS.

    Regards,
    Rishabh
  • Hi Rishabh,

    the sdk doc dir only this:

    take the liberty of asking, are you in America now?

    Regards,

    Cesar.

  • Hi Cesar,

    We are referring to two different SDKs: Processor SDK Vision and Processor SDK Linux.
    I will ask the Processor SDK Linux expert to help you.

    Regards,
    Rishabh
  • Hi Cesar,

    The Processor SDK only supports booting the M4 binary which is shipped with the filesystem.
    If you want to develop on the IPU1, you should have a Vision SDK.
    Also, the binary shared by Rishabh should be run with a CCS boot, Do not boot Linux.
    Perform a CCS boot and then load the binaries from CCS

    Regards,
    Nikhil D
  • Hi Nikhil D,

    "The Processor SDK only supports booting the M4 binary which is shipped with the filesystem."
    1. I run the gpio example: csl_gpio_toggle_app_ipu1_0_release.xem4;
    the csl_gpio_toggle_app_ipu1_0_release.xem4 is the M4 binary.
    Why is the serial port not exported?

    2.what is the Vision SDK, how run the examle on the CCS.

    Regards,
    Cesar
  • Hi Nikhil D,

    I read a lot of information,have no idea,
    I was going to crash;

    please you detailed description How to build the environment for about CCS :
    $/linux-devkit/sysroots/armv7ahf-neon-linux-gnueabi/usr/share/ti/ti-pdk-tree/packages/ti/csl;

    Again, let me explain my purpose.

    1. i want to test the ti/csl/gpio on the IPU1, enable the led pin;
    2. i send the led pin status to A15 on the IPU1;

    the problem:

    i don't know build the IPU1 on CCS,
    i don't know build the IPU1 need for environment on CCS.


    thank you very mach.
    Cesar
  • Hi Cesar,

    You need to do the below:
    1. Download Vision SDK (AKA Processor SDK Vision) from www.ti.com/.../PROCESSOR-SDK-TDAX
    2. Go through the CCS training slides to understand how to run a binary via CCS. You can also refer to youtube video I had shared previously.
    3. I am assuming that you have CCS installed on your system. If not kindly download from www.ti.com/.../CCSTUDIO.

    Regards,
    Rishabh
  • Hi Rishabh,

    i download the VERSION SDK, and next step,how test gpio example and connect the dra725-evm board;

    Regards,

    Cesar

  • Hi Cesar,

    Follow the below instructions:
    1. Go to folder ti_components\drivers\pdk_01_08_01_06\packages\ti\build.
    2. Give command "make -s csl_gpio_toggle_app BOARD=tda2ex-evm CORE=ipu1_0". Make sure that compiler path/PDK path is set correctly in Rules.make.
    3. This will create csl_gpio_toggle_app_ipu1_0_release.xem4 in <pdk_rootdir>\packages\ti\binary\csl_gpio_toggle_app\bin\tda2ex-evm.
    4. Open CCS. Create a target configuration for TDA2Ex/DRA72x.
    5. Set SYSBOOT to a reserved bootmode. Launch configuration and Connect to A15.
    6. Run Enable IPU gel script.
    7. Connect to IPU1_0 and load the binary and run.

    I really hope this helps.

    Regards,
    Rishabh
  • Hi Cesar,

    For more documentation on CCS refer to the below links:
    processors.wiki.ti.com/.../Category:Code_Composer_Studio_v7
    dev.ti.com/.../
    www.ti.com/.../sprac17b.pdf

    Regards,
    Rishabh
  • Hi Rishabh,

    thank you for your reply,

    i don't find make compiler tool on windows

    Regards,

    Cesar

  • Hi, i use the gmake tool

    make the csl_gpio_toggle_app is nothing, but it'ok that make the dcan

    Regards,

    Cesar

  • Hi Cesar,

    I checked the PDK code base. csl_gpio_toggle_app is validated only for A15 core 0.
    Kindly try the build by using CORE=a15_0. Remaining build command is same.
    If you need M4 binary first you need to port this app on M4.

    Regards,
    Rishabh
  • Hi Rishabh,

    i find our product(dra72x) is not supported the version sdk,we use the sdk 'ti-processor-sdk-linux-automotive-dra7xx-evm-03_02_00_03';
    the sdk have 'make ipc_ipu' , build out './component-sources/ipc_3_43_03_05/packages/ti/ipc/tests/bin/ti_platforms_evmDRA7XX_ipu1'
    to load the example 'messageq_single.xem4'

    # cd/sys/bus/platform/drivers/omap-rproc/
    # echo 58820000.ipu > unbind
    # echo 58820000.ipu > bind
    success load:
    [ 99.666729] remoteproc0: Booting fw image dra7-ipu1-fw.xem4, size 3910020
    [ 99.674012] omap-iommu 58882000.mmu: 58882000.mmu: version 2.1
    [ 99.693495] remoteproc0: remote processor 58820000.ipu is now up
    [ 99.700611] virtio_rpmsg_bus virtio0: rpmsg host is online
    [ 99.707160] remoteproc0: registered virtio0 (type 7)
    [ 99.713517] virtio_rpmsg_bus virtio0: creating channel rpmsg-proto addr 0x3d

    but i want get the gpio state from ipu to A15, how operate on ipu; i find the pdk example, but load it can't work;

    Regards,
    Cesar
  • Hi Cesar,

    I did not exactly understand what you are looking for. As I stated previously gpio toggle example is not supported on M4.
    You need to first port the example and then try. The application won't work directly.

    Regards,
    Rishabh