Hi
My tools:
OS: win7
Board: customized
DSP: C6678
FPGA: Virtex 7
CCS: 7
I studied "sprugw1b.pdf" and I have some question about that.
Q1:
What is the meaning of number 2 and 3 bitfields of register PER_SET_CNTL1 at page 164? ( Is the SYS_CLOCK source from TX port?)
I set the Peripheral at the 3.12Gbps rate and checked the "SPn_CTL2" register values.
The value of fields " BAUD_SEL" and "GB_3p125_EN" were zero (register SP(n)_CTL2 at page 214).
Q2:
Is the value of fields " BAUD_SEL" and "GB_3p125_EN" correct?
In my application FPGA send data to DSP and DSP after some processing sends data back to FPGA. I checked the "SP_GEN_CTL" register values(page 212).
The console prints were:
Q3:
I don't know what should be the value of "SP_GEN_CTL" register according to my application?
Q4:
What is the meaning of number 2 bitfields of register "LANEn_STAT0" at page 233?
Best Regards
