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AM3354: TPS65217 1.8V power-up question

Part Number: AM3354

Hi Team,

Recently, when my customer wants to use the TPS65217C to power up AM335x, they're trying to understand the power up sequencing of the TPS65217C.

It tells that the LDO3 is powering up after the DCDC1. The LDO3 is 1.8V power rail. the DCDC1 is the VDDS_DDR power rail.

According to the AM335x power up sequencing, the 1.8V Power rails should powered up before the VDDS_DDR.

So is this LDO3 a violation?

  • Hi,

    Steven Liu1 said:
    According to the AM335x power up sequencing, the 1.8V Power rails should powered up before the VDDS_DDR.

    I don't see any such requirement in the AM335x Datasheet. TPS65217C is a PMIC designed to meet the AM335x power requirements and has been successfully used by customers for quite some time. We have had no complaints about power sequencing so far.

  • Hi Biser,

    Thanks for your reply!

    I agree with your point that the design has been used for a long time without any issue reported from customers. Just curious about the power up sequencing requirement of the AM335x. According to the power up sequencing requirement of AM335x datasheet, all 1.8V supplies should be ramp up before or simultaneously VDDS_DDR as shown below, is that the timing requirement of the AM335x?

    But why in the TPS65271C design, some 1.8V supply(like the LDO3) is after the VDDS_DDR?

       

  • I believe the PMIC is configured with only 1ms delay between Strobe 1 and Strobe 2. Because the LDO is much faster to turn on and the SMPS has some internal start-up delay, the result is they both ramp at the same time and at the same transition rate. This has been verified in oscilloscope captures. Does that clear up your question?