CCS/AM3352: DDR3 timings issue

The DDR experts have been notified. they will respond here.

Andy

#1 Can you share your report? If you cannot share this in the forum, please contact the local FAE so we can get it in the factory here
#2 tIS is measured at the memory input pins - is your setup measuring the Clock and Address line at the same point?
#3 Have you followed all the layout guidelines as documented in the data sheet including topology, length/skew constraints etc.?

Regards, Siva

Hi, Siva,

Thank you for the reply.

1. OK, I will share it latter.
2. tIS, tIH are measured at the memory input pin. Both clock and address signals are probed on the memory side. The probe is placed at the PCB via right next to the BGA ball (less than 10 mils) under the DDR chip.
3. Yes, I followed it. In my project, only one DDR is used, so it connects to CPU directly. clk/ add/ dq/ dqs are routed at 1.2 inches, clk/ add skew are limited at +-100mils.

7455.ddr_tih_fail.pdf

here is part of the report.

Thanks for sharing the report. I'll go through and send my feedback.

Regards, Siva

Andy

Thanks for providing the report.

In your configuration you provided, you have:

#define CMD_PHY_CTRL_SLAVE_RATIO 0x80
#define CMD_PHY_INVERT_CLKOUT 0x1

#define DATA_PHY_RD_DQS_SLAVE_RATIO 0x38
#define DATA_PHY_FIFO_WE_SLAVE_RATIO 0xFA
#define DATA_PHY_WR_DQS_SLAVE_RATIO 0x8B
#define DATA_PHY_WR_DATA_SLAVE_RATIO 0xC5

You need to change

from:
#define CMD_PHY_CTRL_SLAVE_RATIO 0x80
to:
#define CMD_PHY_CTRL_SLAVE_RATIO 0x100

Please verify timing with this change and let me know what you find

Regards, Siva

Hi, Siva,
Before I posted my question here, I have tried several values of CMD_PHY_CTRL_SLAVE_RATIO, 0x100, 0x60, 0x40, 0x0.
But none of them changed the hold time. The waveform were almost identical.

Andy,

Can you share all the registers you changed? It is key to have invert_clk setting and the PHY_CTRL together as below:

#define CMD_PHY_CTRL_SLAVE_RATIO 0x100
#define CMD_PHY_INVERT_CLKOUT 0x1

Can you verify this in your SW? If the behavior is still the same, I'm not sure if you have a HW/board issue.

Regards, Siva

Hi, Siva,

Thank you for the reply. Here is my setting:

#define CMD_PHY_CTRL_SLAVE_RATIO 0x80 // Tried 0x100, 0x60, 0x40, 0x0.
#define CMD_PHY_INVERT_CLKOUT 0x1

#define DATA_PHY_RD_DQS_SLAVE_RATIO 0x38
#define DATA_PHY_FIFO_WE_SLAVE_RATIO 0xFA
#define DATA_PHY_WR_DQS_SLAVE_RATIO 0x8B
#define DATA_PHY_WR_DATA_SLAVE_RATIO 0xC5

#define DDR_IOCTRL_VALUE (0x18B)

#define ALLOPP_DDR3_READ_LATENCY 0x207 // ODT turn on
#define ALLOPP_DDR3_SDRAM_TIMING1 0x0AAAE51B
#define ALLOPP_DDR3_SDRAM_TIMING2 0x2C5EFFBA
#define ALLOPP_DDR3_SDRAM_TIMING3 0x501F82BF
#define ALLOPP_DDR3_SDRAM_CONFIG 0x61C04A32
#define ALLOPP_DDR3_ZQ_CONFIG 0x50074BE4

#define ALLOPP_DDR3_REF_CTRL 0x00000C30 //400 * 7.8us

I also tried inverting the clock, or changing the CL from 6 to 5 (a little unstable).

#define CMD_PHY_CTRL_SLAVE_RATIO 0x80
#define CMD_PHY_INVERT_CLKOUT 0x0

#define DATA_PHY_RD_DQS_SLAVE_RATIO 0x3B
#define DATA_PHY_FIFO_WE_SLAVE_RATIO 0x9d
#define DATA_PHY_WR_DQS_SLAVE_RATIO 0x36
#define DATA_PHY_WR_DATA_SLAVE_RATIO 0x74

Andy,

Are you still noticing the timing violations with these settings? If so, I think you need to review if your layout is meeting all the skew requirements per the data sheet and/or review test setup.

I'm unable to comment what other specific issue could be causing the timing violation here.

Regards, Siva

Andy

Do you have any other questions? I've not received any further information from you on this issue. Please update the latest status and if the issue is still open.

Regards, Siva