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DRA756: Timer PWM Output Jitter

Eric Best
Expert 7725 points

Part Number: DRA756

Hi,

I am investigating using the DRA75x timer PWM outputs (in toggle mode) for secondary system clocks in the 500kHz to 2MHz range.  These signals ideally need to be fairly low jitter (<=1nS).  The assumption is that the timer outputs will be synchronous to the L4 Peripheral clock.  So looking for any information regarding jitter of these outputs.  For example, if using sysclk1 at 20.0MHz as a clock source to the timer, and L4 peripheral clock is at 133MHz, will the timer output be subjected to 7.5nS of jitter (1/133.3MHz)?

Thanks,
Eric

  • 0
    TI__Mastermind 25070 points

    Hi Eric,

    I think timers run off the functional clock selected as described in section CM_CORE_AON_TIMER Overview.

    L4 clock should not effect the timer performance or I'm missing something?

    Regards,

    Stan

  • 0 in reply to Stanislav Stilyanov
    TI__Expert 7725 points

    Hi Stan,

    Thanks for the response.  That is the verification that I am looking for.  So you are saying that the L4 peripheral interface clock will not affect the Timer PWM output jitter (i.e. no qualification to the L4 clock from the timer block to the outputs).  Thus, any jitter component would be restricted to the functional clock alone (and associated internal circuitry related to the functional clock). 

    Thanks,
    Eric

  • 0 in reply to Eric Best
    TI__Mastermind 25070 points
    Eric,
    Yes, the timer counter works off the functional clock (subject to select from several sources). L4 clock is needed for register access and according to TRM, L4 clock even can be paused for power savings and timer can generate wake-up requests at the same time (upon overflow or other event).

    Regards,
    Stan