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RTOS/AM5728: PCIe MSI address mapping

Manjula KS
Intellectual 430 points

Part Number: AM5728

Tool/software: TI-RTOS

Hi,

I have a setup where AM572x DSP core side runs RC and FPGA runs EP. Now FPGA sends MSI interrupts and in RC i need to handle it.

I am provided some details of FPGA MSI capability as below

Descriptor name           offset             value

 CapID                            0x50              0x5

 Next Pointer                   0x51             0x78

 Message Control           0x52             0xA5

Message Address          0x54              0xFEE0F00C

Message Upper Address 0x58             0x0

Message Data                 0x5C             0x49B4

From this I understand that FPGA is MSI enabled, the MMC[19-17] of Message control field is 2 which means FPGA can send 2 MSI interrupts over the address 0xFEE0F00C and data 0x49B4

How should i configure MSI address in my RC code. MSI messsages are handled through any PCIE INBOUND address region? Which address space MSI messages are exchanged.

Is it sufficient if I program MsiCtrlAddr register with address 0xFEE0F00C?

How do i differentiate the 2 MSI interrupts from the RC FPGA?

In the Ti Example code for PCIE, in the PlatformSetupMSIAndINTX function, RC msiCtrlAddr is programmed PCIE_WINDOW_MSI_ADDR and EP MsiLowAddress is PCIE_WINDOW_MSI_ADDR>>2

and in the PlatformMsiIntxIsr isr function if (msiBits[0].msiCtrlIntStatus == 1) means that RC has received MSI interrupt

MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with
N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]
I am assuming that MSI vector differentiates the MSI interrupts 1 & 2

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 430 points

    Please give me update on this

  • 0 in reply to Manjula KS
    TI__Guru* 95265 points
    Hi,

    MSI interrupt is basically a memory write transaction. First you need to make sure both RC and EP could initialize and accept the memory access by enabling the BUS_MS and MEM_SP bits in Status and Command Register on both RC and EP sides.

    Then you need to do the memory write on EP side (write message data to message address) to have the MSI packet over the PCIE link. On the RC side, you need a BAR configuration to accept incoming address like 0xFEE0F00C. Also, programing MsiCtrlAddr register with address 0xFEE0F00C.

    MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with
    N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]
    I am assuming that MSI vector differentiates the MSI interrupts 1 & 2 ====> This is correct.

    Regards, Eric
  • 0 in reply to lding
    Intellectual 430 points

    Can you please tell me how do I configure Bar to accept incoming MSI addresses (the MSI address 0xFEE0F00C)

    Why I need this info let me explain.

    I have the setup like this. I have AM5728. DSP core runs TI RTOS as RC and I have a FPGA as end point. and RC trigger send and receive of data to/from FPGA using EDMA in two different pcie address spaces. 

    So i know that i have to configure two OB ATU to send and receive data from FPGA. Since RC receives MSI messages, i want to know how to do BAR configuration for accepting MSI addresses

    Also,

    I am assuming that the AM5728 ARM side which runs Linux rtos, does the enumeration of RC and EP. Now how should i do bar configuration for MSI messages?  

    If otherwise, suppose ARM linux does not do the enumeration and RC should be self configured (as in the example code provided in TI PCIE drv example. In the example code both RC and EP are self configured), I dont know how to configure FPGA from RC.

    So kindly let me know in my case what is feasible. ARM should take care of enumeration or the DSP RC code should do self configuration and also configuration of FPGA end point?

    Kindly reply me at the earliest.

    Thanking you.

    Regards

    Manjula

  • 0
    Intellectual 430 points

    Part Number: AM5728

    Tool/software: TI-RTOS

    Hi,

    In have to receive data over EDMA after I receive the MSI interrupt. This receiving of data from FPGA has to happen in the bottom half ISR.

    So how do i create task and wait on semaphore pend so that when i get MSI interrupt I can do semaphore post and the my task can takeover reading the data

  • 0 in reply to Manjula KS
    Intellectual 430 points

    Kindly update me on this.

    One on the MSI configuration.

    Second is creating tasks in the driver to perform EDMA receive in the bottom half ISR.

  • 0 in reply to Manjula KS
    Intellectual 430 points

    Anybody please update on this. It will help my further implementation.

  • 0 in reply to Manjula KS
    TI__Guru* 95265 points
    Hi,

    The RTOS PCIE code doesn't do the enumeration. So the DSP running as RC can't configure the FPGA running as EP. They have to be configured separately.

    If you run Linux on A15, the Linux OS can enumerate PCIE EP so to configure the FPGA. I believe Linux should be able to read the FPGA's MSI capability registers and set-up a BAR and inbound translation to accept the MSI interrupt came in.

    For semaphore pend/post implementation, you can look at processors.wiki.ti.com/.../BIOS_Training:_Semaphores
    www.youtube.com/watch

    software-dl.ti.com/.../Semaphore.html

    Regards, Eric