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66AK2E05: About DQS/CLK skew failed Issue

yimin bai34
Genius 4755 points
Part Number: 66AK2E05

Hi Sir

DQS/CLK skew failed probed on SO-DIMM connector as following picture for you reference.

There is no length matching rule for DQS/CLK in “keystone DDR3 length rules template” and EVM board.  

Is any parameter setting in K2E can solve this issue or any solution to test this failed item?

BR

Yimin

  • 0
    TI__Guru**** 161600 points
    Hi,

    I've notified the design team. They will post their feedback directly here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Mastermind 46460 points

    Yimin,

    All JEDEC timing values are defined at the balls under the SDRAM.  They cannot be measured at the UDIMM connector.

    There is no such PCB track length matching requirement for DQS to CLK.  DDR3 topologies are routed in a fly-by topology.  This is discussed in the KeyStone DDR3 Layout Guidelines and in much literature.  The fly-by routing enables the speeds that DDR3 runs.  Since fly-by routing results in significant delay variation between the CLK and DQS at each SDRAM, the DDR3 Controller and PHY within the KeyStone device must perform Write Leveling to adjust for this delay offset.  Under ideal conditions, after leveling is complete, the CLK and DQS arrive at the SDRAM at exactly the same time.

    Tom

  • 0 in reply to Tom Johnson 16214
    Genius 4755 points

    Hi SIr 

    thanks for your reply. write leveling was enabled with DDR3 measurement.

    It is strange to have big different skew between DQS0 and DQS5 because routing length is 400mils difference as following pictures.

    Could you have any suggestion to improve it? Or any similar experience to share with us?

    BR

    Yimin

  • 0 in reply to yimin bai34
    TI__Mastermind 46460 points

    Yimin,

    Similar to my answer above - there is no required skew alignment between DQS signals on different byte lanes.  The leveling will adjust the DQS signal on writes so that the CLK and DQS arrive at each SDRAM simultaneously.  Please research DDR3 leveling requirements and functionality.

    Tom