• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 98 subscribers
  • Views 391 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DM644x Digital RGB output

Ferhat OLGUN
Expert 1080 points

Hi  to all,

I want to switch the video output to digital RGB 565 or 888 with 480 x 272 resolution in "v4l2 example" runnig on DM6446EVM . Although I changed the parameter  in "video.conf" for that example to output 640x480 LCD output , I think that it is YCbCr output.

How can I configure the parameters

1- Video output color space type (YUV, RGB)

2- Resolution of the video displayed

3- LCD timing parameters

I read the document  "Digital Video Using DaVinci SoC" (SPRAAN0) but it is not for SDK v1.30.  Is there any new version of that document ?

Ferhat

 

  • 0
    TI__Mastermind 37340 points

    480x272 is not natively supported by our Linux drivers, but if you wanted to do a quick test on 640x480, you would simply add the following arguments to your u-boot bootargs variable.

      ' davinci_enc_mngr.ch0_output=LCD davinci_enc_mngr.ch0_mode=640x480 '

    Once you get this working, you can start modifying the driver to support your 480x272 requirement.

  • 0 in reply to Juan Gonzales
    Expert 1080 points

    Now I can get the signals from digital video output and try to modify the driver looking at VPBE document (sprue37c.pdf) . First think I want to do is to divide the 27Mhz VCLK to 9Mhz .  Then changing HSPLS,VSPLS,HINT,HSTART,HVALID,VINT,VSTART and VVALID registers to do modify sync signals.

     

  • 0 in reply to Ferhat OLGUN
    TI__Mastermind 37340 points

    Did you get 640x480 working?  If so, then the steps suggested above are the way to proceed.

  • 0 in reply to Juan Gonzales
    Expert 1080 points

    I just verify the video output signals on scope. Now I try to understand how to generate 9 Mhz VCLK ( PLL2 mode to divide 54Mhz to 9Mhz ,or  using half-rate mode for DCLK)

    Actually I couldn't find any definition for "PLLDIV1" register in kernel files which I need to modify to divide 54Mhz to 9Mhz . Could you please help me to adjust the VCLK frequency ?