Other Parts Discussed in Thread: PCM1864
Tool/software: TI-RTOS
Before we test the K2GEVM board ,we find the configuartion information in realtime_demo_bios is conflictd with《PCM186x 103 dB 2ch and 4ch Audio ADCs With Universal Front End》reference information（page-31）.The Master configurations of PCM1864 in the realtime_demon_bios is as follow:
ret = cmb_pcm186x_write_reg(addr, 0x00, 0x00);
ret |= cmb_pcm186x_write_reg(addr, 0x20, 0x3E); // {0x21, 0x0B}, // PLL to DSP1 Divide value = 1/12
ret |= cmb_pcm186x_write_reg(addr, 0x21, 0x0B); // {0x22, 0x17}, // PLL to DSP2 Divide value = 1/24
ret |= cmb_pcm186x_write_reg(addr, 0x22, 0x17); // {0x23, 0x2F}, // PLL to ADC Divide value = 1/48
ret |= cmb_pcm186x_write_reg(addr, 0x23, 0x2F);
ret |= cmb_pcm186x_write_reg(addr, 0x20, 0x30); // {0x20, 0x30}
ret |= cmb_pcm186x_write_reg(addr, 0x21, 0x02); // {0x21, 0x02}, // XTAL to DSP1 Divide value = 1/3
ret |= cmb_pcm186x_write_reg(addr, 0x22, 0x05); // {0x22, 0x05}, // XTAL to DSP2 Divide value = 1/6
ret |= cmb_pcm186x_write_reg(addr, 0x23, 0x0B);// {0x23, 0x0B}, // XTAL to ADC Divide value = 1/12
ret |= cmb_pcm186x_write_reg(addr, 0x25, 0x17); // {0x25, 0x17}, // PLL to SCK Divide value = 1/24
ret |= cmb_pcm186x_write_reg(addr, 0x26, 0x03);// {0x26, 0x03}, /** SCK to BCK divider to 4 **/
ret |= cmb_pcm186x_write_reg(addr, 0x29, 0x03);// {0x29, 0x03} P Divide value = 1/4
ret |= cmb_pcm186x_write_reg(addr, 0x2a, 0x00);// {0x2a, 0x00} R Divide value = 1
ret |= cmb_pcm186x_write_reg(addr, 0x2b, 0x10);// {0x2b, 0x10} J Divide value = 16
ret |= cmb_pcm186x_write_reg(addr, 0x28, 0x01);// {0x28, 0x01} PLL_REF_SEL=SCK; PLL_EN=Enabled
we cann't figure out Master clock number , Bit clock number and Frame clock nubmer . Is the bit clock offered by the pin of K2G SOC_MCASP1ACLKR( JP1-33 ) ?
We are confused on this problem. We are waiting for your help.
Thank you very much !
Wujun
