AM5728: Shared memory setup in RTOS

Daniel Castagnola Weckesser

Part Number: AM5728
Other Parts Discussed in Thread: SYSBIOS

I have the following scenario:

- Cortex-A15 software based on SYSBIOS
- DSP1 and DSP2 software on baremetal
- A small memory buffer in OCMC_RAM3 to share data among them all

The problem is that the shared buffer works fine only between DSP cores, but I wasn't able to exchange data among A15 and the DSP's. I checked the buffer location in all .map files and they look fine. I guess the problem concerns the A15 cache, DSP MMUs, L3 interconnect, or something like this, but the related documentation is quite cumbersome and I did not find any example to check.

Any idea or example to go on ?

Thanks in advance,
Daniel

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

The RTOS team have been notified. They will respond here.

0 Sahin Okur over 8 years ago

TI__Mastermind 27355 points

Hi Daniel,

We don't have any bare metal examples that match your application, but we do have many examples for IPC that run on TI-RTOS in the Processor SDK. More info can be found here:

Regards,

Sahin

0 Daniel Castagnola Weckesser over 8 years ago in reply to Sahin Okur

Intellectual 410 points

Hi Sahin,

Thank you for your reply.
Unfortunately due to the singularities of this project we can not afford SYSBIOS at the DSP side (long and boring story).
We finally confirmed the suspicion of A15 cache being the root cause of the issue, and provisionally fixed that by invalidating or writing back as neccesary after respectively reading or writing shared locations. Certainly I believe that shared memory should not be cached given that the cache controller of a core is not usually aware of the locations modified by others, but I wasn't able to find a way to configure the MMUs to avoid caching specific memory locations. Could you help me about ?. Thanks in advance.

0 Rahul Prabhu over 8 years ago in reply to Daniel Castagnola Weckesser

TI__Guru** 116780 points

Daniel,

Cache coherency is a major issue with multi-core development environment. This needs to be managed by the application software and is managed by the IPC component (Processor SDK RTOS component). If you are unable to use IPC then you will need to manage the cache as described below for GPP+DSP Environment for the shared region:
processors.wiki.ti.com/.../Codec_Engine_Application_Developers_Guide

If you don`t use cache on the shared location, you may see performance hit in inter processor communication so we recommend you keep the location cached escpecially if you are passing or reading large chunk of data.

Regards,
Rahul

0 Daniel Castagnola Weckesser over 8 years ago in reply to Rahul Prabhu

Intellectual 410 points

Thanks!

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AM5728: Shared memory setup in RTOS