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eCAP output state changes to high instead of low when the LPSC is disabled

Sugumar Natarajan
Intellectual 670 points
Other Parts Discussed in Thread: OMAP-L138

 I am working on the OMAP-L138  evm. In my  evm,  eCAP module output is interfaced to the LCD backlight  and is used to control the  brightness. i am working on the eCAP driver to generate the PWM pulse to control the brightness. With my driver, i am able to vary  the brightness from 0 to 100%. The problem arises  when the  module state of LPSC is set to  'Disable state'   for  0% duty cycle.

 when the  eCAP registers are  configured for  0% duty cycle , Module LPSC is disabled  on the assumption that the output would remain low. Instead,  the output  is going to high. If  a delay (Minimum delay of 10 ms)is introduced  between register write and LPSC disable ,  the output goes to low.

So i have few questions ,

1. why doesn't  the output state remain low  (on 0% duty cycle ) when the LPSC is disabled ?

2 . why does the o/p state  change to low  on inclusion of delay?

3. what would  be the o/p state  if  LPSC is disabled while the eCAP module is functioning with  50% duty cycle (or non-zero value). Will it go to high  or low ?

4. With module LPSC disabled, will the eCAP module still drive the output pin or not?

 

 

 

 

  • 0
    TI__Expert 8785 points

    The purpose of LPSC is for power savings.  When doing LPSC disable, it places the module in a safe state, so it can gracefully stop the module clock.  Most likely, the safe state of the eCAP drives the output pin low.

    Here are some suggestions for 0% duty cycle

    • Using GPIO
      • There is a GPIO pin that is muxed with the eCAP_APWM pin. 
      • Pre-configure the GPIO to output either high or low.  When the pinmux is selected for APWM, the GPIO output does not affect the APWM operation
      • Whenever a 0% duty cycle is needed, you can change the pinmux to allow the GPIO to drive the output pin, instead of the APWM
    • Changing eCAP settings
      • You can select the polarity of ECAP by ECCTL2[APWMPOL].  This field defines the state of the output pin after a compare match
      • Whenever a 0% duty cycle is needed, wait for a compare match, and then stop the time stamp counter, via ECCTL2[TSCTRSTOP].  This will "freeze" the eCAP to whatever state it is in. 

    --Christina

  • 0 in reply to clam
    Intellectual 670 points

    Hi Christina,

       Thanks for your suggestions.  I don't want to go for the first option as it would make my driver to be SOC specific.  I have devised a work around based on the second one. The polarity  has been  set to active low (Compare match defines low value) ; compare match  set to  period cycle + 1 so that the  output is zero for the entire period and then the  counter  is reset to zero so that compare would happen immediately. This has been tested and it is working well.

      Kindly confirm if  this implementation is okay ?

     

    Regards,

    N.Sugumar

     

  • 0 in reply to Sugumar Natarajan
    TI__Expert 8785 points

    That's a good implementation.  There should be no issues with it.

    --Christina