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DRA744: VIP connectiion

Mickey Hu
Intellectual 400 points

Part Number: DRA744
Other Parts Discussed in Thread: DRA714

I want to use a multiplexer changing 24 bits vout source (vou2,vout3) from J6, and using vin3a to receive as loop back test.
Besides data pin D[0:23], clock, hsync. vsync, there are some difference as below
VOUT2: vout2_de
VOUT3: no other pins
VIN3a: vin3a_de0, vin3a_fld0

Question
1. Can I  let vin3a receiving VOUT2 without  vin3a_fld0
2. Can I  let vin3a receiving VOUT3 without  vin3a_de0 & vin3a_fld0

Best Regards
Compal HW engineer
Scorpio
E-mail: Scorpio_Ho@compal.com

  • 0
    TI__Mastermind 42515 points
    Hi Mickey,

    I have forwarded your question to VIP expert.

    Regards,
    Yordan
  • 0 in reply to Yordan Kamenov
    Intellectual 400 points
    Hi Yordan
    My team is working on schematic drawing now, please feedback as soon as possible
  • 0
    TI__Guru**** 499745 points
    hi Mickey,

    fld is required only if you have interlaced input and you could work without de line if you have hsync connected to vip port.

    Rgds,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Intellectual 400 points
    Hi Brujesh
    I have both hsync & vsync, but none fld pin of vout2 & vout3. Is there any way to solve it? I just want to test the interface is no problem

    Another question I need ti comfirm, I saw the description of vout3's ball in datasheet as below
    (1) The VOUT3 interface when multiplexed onto balls mapped to the VDDSHV6 supply rail is restricted to operating in 1.8V mode only (i.e.,
    VDDSHV6 must be supplied with 1.8V). 3.3V mode is not supported. This must be considered in the pin mux programming and
    VDDSHVx supply connections.
    For example,
    vout3_clk, Video Output 3 Clock output, P1 / AF9 (1)
    Is that mean only ball AF9?
  • 0 in reply to Mickey Hu
    TI__Guru**** 499745 points
    Hi Mickey,

    Can you check in the latest DM? I see that this AF9 ball support dual voltage, 1.8V and 3.3V..

    Typically HS/VS signals should be good enough to provide line signals and frame signals, but it depends on the receiving device. Where are capturing these outputs? If the receiver expects de, then you will require de output signal.

    Rgds,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Intellectual 400 points
    Hi Brijesh
    The SoC is mounted on a LGA module designed by costumer, I have to design a fixture.
    The module has both vout2 , vout3 & vin3a functions, we want to test it by loopback connection.
    I need some advise mentioned above, other pins have defined by costumer.
    Therefore, I don't have other pins to define DE for vout2 & FLD for vout2/vout3.
    I just want to ensure that the video interface is OK.
  • 0 in reply to Mickey Hu
    TI__Guru**** 499745 points
    Hi Mickey,

    So you want to try reverse loopback, ie you want to send some data over vout and capture it through vin. correct?
    hs and vs control signals (in addition to data and clock signals) are sufficient to get the video captured by vin. fld is required only if the display requires to be interlaced and DE is required only if you want to capture active video. Please check with the customer which signals are required.

    Rgds,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Intellectual 400 points
    Hi Brjesh
    Your interpretation is correct.
    So I can send "RGB888" format by D[0:23], hs/vs, & clock by DRA714(vout2) or DRA744(vout2 & vout3) to vin3a
    without de & fld as loopback, correct?
    I use 2pcs SN74CBTLV16292VR as switches to select D[0:23] of vout2/vout3, it is 12 pins/pc.
    And the rest 3 pins are hsync, vsync & clock, can I choose another part TS3A27518EIRTWRQ1.
    Is there any effect choosing different switch? Or I need add the third SN74*?
  • 0 in reply to Mickey Hu
    TI__Guru**** 499745 points
    Hi Mickey,

    Yes, HS/VS, D[0:23], clock lines should be good enough. But again, it really depends on the your display requirement..
    I will not be able to help in hardware selection. You could contact your local TI FAE to help you out.

    Regards,
    Brijesh
  • 0 in reply to Brijesh Jadav
    Intellectual 400 points

    Hi Brijesh
    Could you explain the waveform of fld pin more?
    Maybe I can reserve a gpio for it, but I will not make it working at the begining.

  • 0 in reply to Mickey Hu
    TI__Guru**** 499745 points

    Hi Mickey,

    For the interlaced output, the entire frame is divided into odd and even lines and transmitted first even lines and then odd lines. For example, first 0, 2, 4, 6... lines and then 1, 3, 5 ,7 ,9... lines. fld pin indicates whether transmitted field contains odd lines or even lines. so it remains active or inactive during entire field, ie almost half of the frame time period..

    Regards,

    Brijesh