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Simultaneous access of shared memory in 6472

AC53351
Intellectual 370 points

Hello,

Can two or more different cores in 6472 read/write simultaneously from different locations in the shared L2 memory? If yes, then where should I find the necessary information?

 

Regards,

AC.

 

  • 0
    TI__Mastermind 18146 points

    Hi AC,

    the answer is yes. The Shared L2 is:

    • Optimized for prefetchable memory reads
    – Speculative prefetching
    – 0 wait state prefetch hits at max CPU clock = 500 MHz
    – Selectable prefetchable and non-prefetchable memory region

    • LRU-based arbitration per bank ARB (The shared memory has 4 banks.)

    • Optimized for single streamer writes

    • Atomic access support

    The document you're looking for is here:

    http://focus.ti.com/lit/ug/sprueg5d/sprueg5d.pdf

    Kind regards,

    one and zero

  • 0 in reply to one and zero
    Intellectual 370 points

    Thank you for your prompt reply........

     

    Regards,

    AC.