Programming the PLL on the DM368

John Anderson

We have recently gotten our own DM368 board up and running. I'd like to get the clocks programmed up to the speced speeds. I'm using the DVSDK_4 beta and there appears to be no support in the UBL for the DM368 higher speed clocks. Is this information available at this time?

I am currently looking at changing the registers myself, but considering that there are so many sub-systems dependant on the clock outputs I'm afraid I may break something in the process, and my time could be much better spent working on other issues. After a search of the forum I'm actually surprised that I'm the first person asking this question . Either everyone else knows what to do or I'm on the bleeding edge of needing to know.

So how about a discussion of programming PLL clocks for the DM368? Any help would be greatly appreciated.

John A

over 14 years ago

0 John Anderson over 14 years ago

Genius 5240 points

Well I found something in SPRS686AA.PDF section....

3.3.6 PLL Controller Clocking Configurations Examples

This section describes the setting up of the PLLs. I'll let you know how it goes.

FYI: The current speed as built by the DVSDK for the DM365 (no selection for the DM368) is 243MHz.

John A

0 John Anderson over 14 years ago in reply to John Anderson

Genius 5240 points

Turns out that speeding up the clocks is not too hard, but the problem is setting up the parameters for the DDR2. Has anyone successfully sped up their DDR2 to 340MHz?

Note: this tripped me up at first. In order to get 340MHZ from the DDR clock line you need to set the PLLDIV (SYSCLK3 or SYSCLK7 depending on PLL selection) to run at 680MHZ. The comment in the code says divide by 2, but the divider is not dividing by 2. It is labeled "DDR 2x Clock", so I guess that's a clue.

John A

0 Sonia Ghelani over 14 years ago in reply to John Anderson

TI__Intellectual 1230 points

John,

Thanks for your question. We are currently working to integrate the UBL support for DM368 in an upcoming DVSDK patch release planned for early December. In the meantime, the team is working to provide the standalone UBL configuration settings on the wiki to DM368 customers who wish to use SDK4 (which will be released in a few weeks’ time). We will post the URL to this wiki as soon as it is completed shortly.

Regards,

Sonia

0 John Anderson over 14 years ago in reply to Sonia Ghelani

Genius 5240 points

Turns out that we have purchased a DVR SDK that contains code for the DM368. I was able to find satisfactory settings to speed the DDR to 340MHz and have it working now. Looking forward to a final release of the SDK and support for the DM368.

John A.

0 Sonia Ghelani over 14 years ago in reply to John Anderson

TI__Intellectual 1230 points

Here is the wiki article that explains the DM368 UBL change settings from the DM365. This will enable users to use the DVSDK (version 3.10+) and codecs, which currently supports DM365.

http://processors.wiki.ti.com/index.php/DM36x_to_DM368_NAND_UBL_porting_guide

I hope this helps.

Regards,

Sonia

0 John Anderson over 14 years ago in reply to Sonia Ghelani

Genius 5240 points

Thanks for the link to that article. My only suggestion would be that the comments regarding the dividers are not correct. The peripheral clock control register selects which PLL is sent to each clock. The comments are confusing because they indicate multiple PLL's controlling the same clock w/ conflicting frequencies

John A

0 Prakash PM over 14 years ago in reply to John Anderson

TI__Intellectual 1275 points

Thanks John for your suggestions. I have updated the wiki accordingly.

-Prakash

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Programming the PLL on the DM368