Hello.
I found that in AM3517 quick manual there is a mistypo.
Table 4-4. 32-kHz Input Clock Source Timing Requirements is written:
tR(32k) Rise transition time, sys_32k max = 20 ns
tF(32k) Fall transition time, sys_32k max = 20 ns
But in LogicPD schematic is used ASEK-32.768kHz which has 40ns.
How can it be or maybe it is not 20ns, but 200ns ?
Also, Table 4-2. 26Mhz sys_clk Input Clock Timing Requirements (continued) is written:
tt(xtalin) Transition time, max = 5 ns
sys_xtalin
But in LogicPD schematic is used AP3S2-26.0Mhz which has 6ns.
Thank you.