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RXMOFOVERFLOW on DM6446

Evan Van ***
Prodigy 10 points

Normal 0 false false false EN-US X-NONE X-NONE

We are utilizing a DaVinci DM6446 chip, which is talking to a Vitesse VSC7395 network switch over MII running at 100Mbit/sec utilizing the DM6446's EMAC module.  We are losing packets due to Middle-of-Frame (MOF) overruns on the Receive side on the DM6446 chip.  Specifically, the DM6446's RXMOFOVERRUNS register is incrementing, but the RXSOFOVERRUNS and RXDMAOVERRUNS registers remain at 0.  Based on TI's documentation, this indicates an overrun in the EMAC's FIFO.

Is there anything that we can do to either prevent, or reduce the occurrence of, these overruns?  We have relatively low traffic at the moment, but are seeing 20-40 of these overruns an hour.  Needless to say, we are concerned with the number of drops when the interface is more utilized.

Thanks for any help that might be forthcoming!

  • 0
    TI__Guru 62975 points

    Evan,

    If you are experiencing FIFO overflows when DMA buffers are available, this may be because the EMAC is not able to move data from the Rx FIFO into the DMA buffers fast enough.  This can happen because of competition with other tasks/hardware for system bandwidth.

    Can you try to increase the EMAC bus priority and/or lower the starvation threshold on shared resources (like PBBPR for DDR)?

    -Tommy