EDMA

Hi! Someone know how can I use EDMA without API??

Thanks!

Hi Marcio

When you set QCHMAP0 in step 1b, you are not programming the TRWORD (or keeping it at default 0), because of this when you write to PARAM0_OPT field it should "trigger" the transfer , as a TRWORD =0 implies PARAMENTRY word 0 (OPT field) would be the trigger word.

You can change 1b to what you have in 4b (configure PARAM entry and TRWORD as 7 in step 1b itself), and then when you do Step 2, your last write to CCNT (PARAM Entry word 7) , should automatically trigger the transfer.

Can you give this a shot.

Regards

Mukul

Hi Mukul!

I tryed to change the 1b to what I have in 4b, but nothing happened....

There are something wrong because the CCERR come with 0x07... and I cant to clear it! I set the register CCERRCLR, but the CCERR come always with 0x07.... some ideia?

Thanks to help!!

Marcio

Hi Marcio

Did you try the alternate sequence from a clean slate i.e. at least with a power on reset etc, from your previously tested sequence.
Can you make sure that prior to setting up the transfer etc, SER/SERH registers are not set?

If you are seeing CCERR set to 0x7 it implies that somehow you are exceeding the thershold for number of events in Q0/Q1/Q2. Default is 16 events at any given instance, are you somehow submitting more events then 16 (I have not seen that happen even in fully loaded systems)? Alternatively, is your code changing the default values of the QWMTHRA register , that sets the default max to 16 events. If somehow this register was being tweaked to set the value to a lower value, then you could get the CCERR for lower number of events queued up in Q0/1/2 etc.

Hope this helps.

Regards

Mukul

Hi Mukul!

You are right about the QWMTHRA register! I cleared this register! But, I cant do the transfer yet....

I think fault to configure some registers yet.... some idea?

Thanks for help!!

Marcio

Marcio

What is your L2 address (what do you see in the PARAM location), and can you also ensure that you are using PARAM0 location (0x01c0 4000?)

Regards

Mukul

Hi Mukul!

Sorry, the PARAM0_DST is 0x80A00000, it is not into the L2 yet. But I think it is not a problem here.

And the PARAM0 location is on 0x01C04000, because I can see the values changing at the "View - Registers - (EDMACC)".

Thanks!

Marcio

Hi Marcio

The steps that you have shared (with 4b mods done to 1b) should've been adequate to get this QDMA transfer working. I don't see anything wrong. Can you share your code or tell me if you are doing something else (like you were erroneously clearing up QWMTHRA etc) that I should be aware of.

Is the test being done on simulator or actual device/EVM etc. Is the external memory initialized?

If you want you can try a simple example with QDMA , with both source and dest linearly incrementing (even though the illustrated example in the user guide should work too).

Something like

        PARAM0_OPT = 0x0C;   // no interrupt
        PARAM0_SRC = (unsigned int)&dataOnDDR;
        PARAM0_B_A_CNT = 0x00040004 ;
        PARAM0_DST = (unsigned int)&dataOnL2;
        PARAM0_D_S_BIDX = 0x00040004    ;
        PARAM0_BCNTRLD_LINK = 0x0000FFFF;
        PARAM0_D_S_CIDX = 0x00100010    ;
        PARAM0_CCNT = 0x01;

simple ACNT=4, BCNT=4 , CCNT=1 with linearly incrementing source and destination indices.

Regards

Mukul

Hi Mukul!

I was testing with my own board, but now I am trying with EVM6437.
I am using the video_loopback.pjt. I just modified the .cmd file. (all the program into DDR).
I put your example between /*setup Back-End*/ and /*wait for the USER to press something*/ , and nothing happened....
Dont I need to initialize something? Like clear all PARAM, set some register/ event?

Thankyou!

Hi!

I noticed 2 registers changed after your example!

ER = 0x3000 0000
QSTAT_0 = 0x0001 0001

I cant understand why the events 29 and 28 asserted?!

Sorry, the ER I resolved! Now, after the example, it is ER = 0x00 !!

Thankyou Mukul! It works!

Was my fault! I didnt see the 2 bytes changed! Sorry!
But I have more one question! What the register I need to see for the transfer complete? I saw just the QSTAT_0 changed....

Thakyou!

Couple of ways to ensure that transfer is done

1) Check the destination buffer address, to see that you are seeing the source buffer content transferred into dst buffer

2) Change the OPT field to enable transfer completion interrupt (TCINTEN=1) , this will set the IPR bit for whatever TCC value you are using (e.g. TCC=0, would set IPR bit 0)

3) You can set the OPT.STATIC=0 (just for experimentation), then if you have Link Field set to 0xFFFF , you will see the PARAM go to null (all fields zero out after transfer is completed).

QSTAT is another good way, but if you have just this one event, and the EDMA is not used for anything else, the first event can bypass the queue, so you might not see the WM change etc. If you are still in trial/error phase, #1 is likely most reliable :).

Regards

Mukul