Using Video DACs as Outputs

Hi,

DSPLINK is used for ARM to DSP communication. If you are looking at accessing a DSS register then you may need to write a linux kernel driver or modify the existing drivers. You don't need DSP/Link for that.

--Sid

Thanks for the response... so a direct driver to the OMAP is the only way to get at the DSS and put it in test mode?  I was trying to avoid that, but I'll give it a shot.  Also,  when you say DSPLink is used for the communication between arm and dsp this means that it does not provide access to the processing that actually occurs on either end but rather allows processing that is done on the arm to be routed to the dsp?

Hi,

A couple of starting pages on the DSP/LINK and Codec Engine may help you get better answers to your question. Please have a look at http://processors.wiki.ti.com/index.php/DSPLink_Overview and http://processors.wiki.ti.com/index.php/Codec_Engine_Overview for an understanding on the same.

--Sid

Some more links at: DSPLink overview
http://processors.wiki.ti.com/index.php/Category:DSPLink
http://processors.wiki.ti.com/index.php/DSPBIOS_LINK_WebEx_Presentations

For your specific query on whether processing can be pushed to DSP, see here: C6Run is a set of tools which will take in C files and generate either an ARM executable, or an ARM library which will leverage the DSP to execute the C code.

and here

Texas Instruments' C6Accel is a free software development tool that allows ARM SoC developers access to production-ready DSP optimized software.

Deepali

Thanks for the link to C6Run ... seems to be doing alot of what I am trying to get CE to do except I dont have to worry about alot of intricacies and can just get C code running on the DSP.  I've got all of the arm executables running from a Beagleboard Rev C4, however when I go to run ./hello_world_dsp, for example I get: 

PROC_load () failed. Status = [0x80008009]
C6RUN_IPC_create() failed!
Segmentation fault

I know 0x80008009 is a DSP_EFAIL and apparently, The DSP executable does not exist at the path provided to PROC_load, but how can I change the path provided to PROC_load?  Is this somewhere in the C6Run/build directory?  Any further information on the 0x80008009 error message would also be helpful since

http://processors.wiki.ti.com/index.php/Troubleshooting_DSPLink_configuration_issues#Problem:_PROC_load_failed_with_DSP_EFILE_error

and

http://processors.wiki.ti.com/index.php/Understanding_DSPLink_error_codes

seem to give very little information.

Thanks

C. Grispino said:

I know 0x80008009 is a DSP_EFAIL

sorry, I mean DSP_EFILE error, not the general DSP_EFAIL

Grispino,

DSP_EFILE means the file that the DSPLink API PROC_load is supposed to load is not available at the path specified in the API.

The solution would be to copy the file in the file system at the path specified or update the PROC_load call API to provide the path where you know the file is present, rebuild the app and re-run it. You will need to grep the code for location of file where PROC_load call is present.

Deepali

C. Grispino said:

sorry, I mean DSP_EFILE error, not the general DSP_EFAIL

It seems strange that you would get this error since with C6Run the DSP executable is not coming from a file, but rather from a binary blob in memory. Can we assume that all required kernel modules have been properly loaded?

Regards, Daniel

Yes, all of the modules have been loaded ... Yesterday, I was actually able to get passed this error by changing/customizing the memory map.  At this point, however, I am running into some problems sporatically when running the examples & tests.  For example, running hello_world will randomally return back (along with Hello World, From 6CApp!): 

DSP MMU error fault [0x1]:  Virtual address reference that generated interrupt: 0xXXXXXXXX.  

Where the Hex number is not always the same for the same executable (examples being 0xe3200008 and 0xe10080c8 for hello_world).  For the time being I have ignored the error because the example is still running and I am getting the response back.  Another strange thing is that not every examples does this.  For example cfft_dsp works with no MMU error, but exit_value always bricks the begleboard, no matter what memory map I am using.

Perhaps you can elaborate on the C6Run command line flag, "--C6Run:save_dsp_image."  I added this to all of the make files to verify what memory maps where being used at compile time, and suprisingly the maps were different than what I had setup in:  $(DSPLINK)/dsplink/config/all/CFG_OMAP3530.c, $(DSPLINK)/dsplink/dsp/inc/DspBios/5.XX/OMAP3530/dsplink-omap3530-base.tci, and $(C6Run)/platforms/beagleboard/platform.tci, yet all of the .map files were the same in relation to each other.  I then changed all three of these files to match what --C6Run:save_dsp_image had said the map was, but running the executables gave a PROC_attach 0x8000800c error code.  I switched the memory map back to the case where I get the sporatic MMU errors since this is the only way I can get executables to PROC_attach and PROC_load.  I guess what I am asking is can you speculate why I keep getting these MMU errors and/or why the memory map I define in the files is different than what save_dsp_image gives?

Thanks,

Christine

For reference, below are the parts of the memory map related files that I changed which eventually caused the PROC_attach (0x8000800C) error:

$(DSPLINK)/dsplink/config/all/CFG_OMAP3530_SHMEM.c :

/** ============================================================================
 *  @name   RESETCTRLADDR
 *
 *  @desc   Indicates the start address of Reset Ctrl memory region.
 *          last two nibbles must be zero i.e. align to 256 boundary.
 *  ============================================================================
 */
#define  RSTENTRYID         0u
#define  RESETCTRLADDR      0x8900000u
#define  RESETCTRLSIZE      0x80u

/** ============================================================================
 *  @name   CODEMEMORYADDR/CODEMEMORYSIZE
 *
 *  @desc   Indicates startaddress/size for dsplink code region.
 *  ============================================================================
 */
#define  CODEENTRYID        1u
#define  CODEMEMORYADDR     (RESETCTRLADDR + RESETCTRLSIZE) //0x89000080
#define  CODEMEMORYSIZE     0xB2FF80

/** ============================================================================
 *  @name   SHAREDENTRYID/SHAREDMEMORYADDR/SHAREDMEMORYSIZE
 *
 *  @desc   Indicates startaddress/size for dsplink shared memory region.
 *  ============================================================================
 */
#define  SHAREDENTRYID0     2u
#define  SHAREDMEMORYADDR0  (CODEMEMORYADDR + CODEMEMORYSIZE) //0X89B30000
#define  SHAREDMEMORYSIZE0  0x80000u

/** ============================================================================
 *  @name   SHAREDENTRYID/SHAREDMEMORYADDR/SHAREDMEMORYSIZE
 *
 *  @desc   Indicates startaddress/size for dsplink shared memory region.
 *  ============================================================================
 */
#define  SHAREDENTRYID1     3u
#define  SHAREDMEMORYADDR1  (SHAREDMEMORYADDR0 + SHAREDMEMORYSIZE0) //0X89BB0000
#define  SHAREDMEMORYSIZE1  0x80000u

/** ============================================================================
 *  @name   POOLMEMORYADDR/POOLMEMORYSIZE
 *
 *  @desc   Indicates startaddress/size for dsplink POOL memory region.
 *  ============================================================================
 */
#define  POOLENTRYID                   4u
#define  POOLMEMORYADDR     (SHAREDMEMORYADDR1 + SHAREDMEMORYSIZE1) //0X89C30000
#define  POOLMEMORYSIZE     0x000D0000u

/** ============================================================================

..

..

..

5,                     /* ENTRY          : Entry number */
"DSPIRAM",             /* NAME           : Name of the memory region */
0x5c7f8000,            /* ADDRPHYS       : Physical address */
0x107f8000,            /* ADDRDSPVIRT    : DSP virtual address */
(Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
0x00008000,            /* SIZE           : Size of the memory region */
TRUE,                  /* SHARED         : Shared access memory? */
FALSE                  /* SYNCD          : Synchornized? */

...

7,                     /* ENTRY          : Entry number */
"DSPL1DRAM",           /* NAME           : Name of the memory region */
0x5cF04000,            /* ADDRPHYS       : Physical address */
0x10F04000,            /* ADDRDSPVIRT    : DSP virtual address */
(Uint32) -1,           /* ADDRGPPVIRT    : GPP virtual address (if known) */
0x00004000,            /* SIZE           : Size of the memory region */
TRUE,                  /* SHARED         : Shared access memory? */
FALSE                  /* SYNCD          : Synchornized? */

$(DSPLINK)/dsplink/dsp/inc/DspBios/5.XX/OMAP3530/dsplink-omap3530-base.tci:

/*  ============================================================================
 *  Load assert support
 *  ============================================================================
 */
utils.importFile("assert.tci");

/*  ============================================================================
 *  Load base TCI file.
 *  ============================================================================
 */
utils.loadPlatform("ti.platforms.evm3530");

/*  ============================================================================
 *  Enable common BIOS features used by all examples
 *  ============================================================================
 */
bios.disableRealTimeAnalysis(prog);
bios.enableMemoryHeaps(prog);
bios.disableRtdx(prog);
bios.enableTskManager(prog);

/*  ============================================================================
/*  ============================================================================
 *  GBL
 *  Enable 32K of L2 cache, 32K of L1D cache and 16K for L1P.
 *  Adjust the size of IRAM, L1DSRAM, L1PSRAM accordingly.
 *  Enable caching for addresses 0x8700_0000 - 0x87FF_FFFF by setting MAR135
 *      MY CHANGE:
 *      IRAM remains 0x8000
 *      L1DSRAM see note in comment below - not defined for 3530
 *      L1PSRAM remains (not on memory maps saved)
 *      Enable 64k of L2 cache, 32k of L1D cache and 32k of L1P
 *  ============================================================================
 */
prog.module("GBL").ENABLEALLTRC        = false ;
prog.module("GBL").PROCID              = parseInt (arguments [0]) ;


prog.module("GBL").C64PLUSCONFIGURE    = true  ;
prog.module("GBL").C64PLUSL2CFG        = "64k" ;
prog.module("GBL").C64PLUSL1DCFG       = "32k" ;
prog.module("GBL").C64PLUSL1PCFG       = "32k";
prog.module("GBL").C64PLUSMAR128to159  = 0x0000C000 ;

var IRAM = prog.module("MEM").instance("IRAM");
IRAM.len              = IRAM.len - 0x8000;

var L1DSRAM = prog.module("MEM").instance("L1DSRAM");
L1DSRAM.len           = L1DSRAM.len - 0x4000;

/* Was defined for sdp3430, but not for evm3530, hence commented
var L1PSRAM = prog.module("MEM").instance("L1PSRAM");
L1PSRAM.len           = L1PSRAM.len - 0x4000;
*/

/*  ============================================================================
 *  MEM
 *  ============================================================================
 */
prog.module("MEM").STACKSIZE = 0x1000 ;

/*  ============================================================================
 *  MEM : RESET_VECTOR
 *  ============================================================================
*/
var RESET_VECTOR = prog.module("MEM").create("RESET_VECTOR");
RESET_VECTOR.base        = 0x89000000;
RESET_VECTOR.len         = 0x00000080;
RESET_VECTOR.space       = "code/data";
RESET_VECTOR.createHeap  = false;
RESET_VECTOR.comment     = "RESET_VECTOR";

/*  ============================================================================

$(C6Run)/platforms/beagleboard/platform.tci:

utils.importFile("dsplink-omap3530-base.tci");

/*  ============================================================================
 *  Memory map variables (must be filled in at config time)
 *  ============================================================================
 */
var DSP_REGION_BASE_ADDR = 0x89000000;
var DSP_REGION_CMEM_SIZE = 0x00C00000;
var DSP_REGION_CODE_SIZE = 0x00100000;


/*  ============================================================================
 *  GBL (MAR bits will be modified at configure time)
 *  ============================================================================
 */
prog.module("GBL").C64PLUSMAR0to31    = 0x00000000;
prog.module("GBL").C64PLUSMAR32to63   = 0x00000000;
prog.module("GBL").C64PLUSMAR64to95   = 0x00000000;
prog.module("GBL").C64PLUSMAR96to127  = 0x00000000;
prog.module("GBL").C64PLUSMAR128to159 = 0x00000200;
prog.module("GBL").C64PLUSMAR160to191 = 0x00000000;
prog.module("GBL").C64PLUSMAR192to223 = 0x00000000;
prog.module("GBL").C64PLUSMAR224to255 = 0x00000000;
prog.module("GBL").C64PLUSL2CFG       = "64k";
prog.module("GBL").C64PLUSL1DCFG      = "32k";
prog.module("GBL").C64PLUSL1PCFG      = "32k";


/*  ============================================================================
 *  MEM : Configuration and adjustment to default config from DSPLink
 *  ============================================================================
 */
var IRAM          = prog.module("MEM").instance("IRAM");
var L1DSRAM       = prog.module("MEM").instance("L1DSRAM");
var RESET_VECTOR  = prog.module("MEM").instance("RESET_VECTOR");
var DDR2          = prog.module("MEM").instance("DDR2");
var DSPLINKMEM    = prog.module("MEM").instance("DSPLINKMEM");
var POOLMEM       = prog.module("MEM").instance("POOLMEM");

/*
 *  Adjust memory regions to sit at the proper location
 */
IRAM.len          = 0x8000;
RESET_VECTOR.base = 0x89000000; //DSP_REGION_BASE_ADDR + DSP_REGION_CMEM_SIZE;
DDR2.base         = 0x89000080; //RESET_VECTOR.base + RESET_VECTOR.len;
DDR2.len          = 0x00B2FF80; //DSP_REGION_CODE_SIZE - RESET_VECTOR.len - DSPLINKMEM.len - POOLMEM.len;
DDR2.heapSize     = 0x00010000; //DSP_REGION_CODE_SIZE/2;
DSPLINKMEM.base   = 0x89B30000; //DDR2.base + DDR2.len;
POOLMEM.base      = 0x89C30000; //DSPLINKMEM.base + DSPLINKMEM.len ;

/*
 *  Set all code and data sections to use DDR2
 */
bios.setMemCodeSections (prog, DDR2) ;
bios.setMemDataNoHeapSections (prog, DDR2) ;
bios.setMemDataHeapSections (prog, DDR2) ;

prog.module("MEM").BIOSSEG    = IRAM;
prog.module("MEM").SYSINITSEG = IRAM;
prog.module("MEM").TEXTSEG    = DDR2;
prog.module("MEM").BIOSOBJSEG = DDR2;
prog.module("MEM").MALLOCSEG  = DDR2;


/*  ============================================================================
 *  TSK : Global
 *  ============================================================================
 */
prog.module("TSK").STACKSEG = DDR2;

also, hello_world_dsp.dsp_image.out

OUTPUT FILE NAME:   <hello_world_dsp.dsp_image.out>
ENTRY POINT SYMBOL: "_c_int00"  address: 107fd7c0


MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  IRAM                  107f8000   00008000  000059a0  00002660  RWIX
  CACHE_L2              10800000   00010000  00000000  00010000  RWIX
  CACHE_L1P             10e00000   00008000  00000000  00008000  RWIX
  L1DSRAM               10f04000   00008000  00000000  00008000  RWIX
  CACHE_L1D             10f10000   00008000  00000000  00008000  RWIX
  RESET_VECTOR          89000000   00000080  00000000  00000080  RWIX
  DDR2                  89000080   00b2ff80  00023a0d  00b0c573  RWIX
  DSPLINKMEM            89b30000   00100000  00000000  00100000  RWIX
  POOLMEM               89c30000   000d0000  00000000  000d0000  RWIX

...

...

...

C. Grispino said:

DSP MMU error fault [0x1]:  Virtual address reference that generated interrupt: 0xXXXXXXXX.  

This was/is an issue related to the shutdown of the DSPLink layer and its message queues.  Some changes were made in 0.94.04.04 to make this go away, and limited testing seemed to indicate it helped.  If you are using this version (or a later version), then maybe there is something further we need to address.

C. Grispino said:

Where the Hex number is not always the same for the same executable (examples being 0xe3200008 and 0xe10080c8 for hello_world).  For the time being I have ignored the error because the example is still running and I am getting the response back.  Another strange thing is that not every examples does this.  For example cfft_dsp works with no MMU error, but exit_value always bricks the begleboard, no matter what memory map I am using.

This is under investigation.  With the current build of the project trunk, I can consistently generate a Linux Kernel Oops from inside the DSPLink kernel driver MSGQ_get function when performing the receipt of the return value and shutdown of the DSP.  I have not yet confirmed if this is an issue with how C6Run uses the message queues orwhether this reflects an issue within DSPLink.

C. Grispino said:

Perhaps you can elaborate on the C6Run command line flag, "--C6Run:save_dsp_image."  I added this to all of the make files to verify what memory maps where being used at compile time, and suprisingly the maps were different than what I had setup in:  $(DSPLINK)/dsplink/config/all/CFG_OMAP3530.c, $(DSPLINK)/dsplink/dsp/inc/DspBios/5.XX/OMAP3530/dsplink-omap3530-base.tci, and $(C6Run)/platforms/beagleboard/platform.tci, yet all of the .map files were the same in relation to each other.  I then changed all three of these files to match what --C6Run:save_dsp_image had said the map was, but running the executables gave a PROC_attach 0x8000800c error code.  I switched the memory map back to the case where I get the sporatic MMU errors since this is the only way I can get executables to PROC_attach and PROC_load.  I guess what I am asking is can you speculate why I keep getting these MMU errors and/or why the memory map I define in the files is different than what save_dsp_image gives?

You should not edit any files within the DSPLink installation. The C6Run build system allows you to change the memory map at platform configuration time.  See this FAQ entry for the suggested way to do this.  If you want to edit files manually, you can make changes to $(C6Run)/platforms/beagleboard/platform.tci, $(C6Run)/platforms/beagleboard/DSPLINK_CFG_update.c, and $(C6Run)/platforms/beagleboard/loadmodules.sh to specify all the memory map settings - just make sure these files all agree with one another.  You may want to experiment with the configure step to see how these three files are affected.

Regards, Daniel