DRA756: EVM DDR VTT Power Enable

Senthil kumar Irulappan

Part Number: DRA756

In the DRA756 EVM i see the DDR VTT Voltage regulator enable is connected to a Processor GPIO (SPI[1]_CS[1]n). What is the purpose / need of this signal? Is this processor GPIO being used to enable the DDR VTT Regulator? Could you pls explain this?

over 7 years ago

0 Stanislav Stilyanov over 7 years ago

TI__Mastermind 18270 points

Hi Senthil,
This pin is actually to disable VTT during low power mode if used.
Kindly refer to TRM section 15.3.4.17 Forcing CKE to tri-state.

Regards,
Stan

0 Senthil kumar Irulappan over 7 years ago in reply to Stanislav Stilyanov

Prodigy 185 points

Thanks Stan for the clarification. This clarifies

0 Senthil kumar Irulappan over 7 years ago in reply to Senthil kumar Irulappan

Prodigy 185 points

Stan, One related query regarding the DDR VTT Enable / Disable. Can you pls explain circuitry involving the Q6 & Q7 in the EVM Design? When the GPIO can be used to disable why we need to use FETs to pull the o/p directly to 0v?

0 Stanislav Stilyanov over 7 years ago in reply to Senthil kumar Irulappan

TI__Mastermind 18270 points

The only reason I can recall is to discharge the filter capacitors faster upon VTT turn off. I'm not an DDR expert and I'm not aware where this requirement came from and if it is manadatory. I guess other schematic solutions may also exist.

Regards,
Stan

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DRA756: EVM DDR VTT Power Enable