DM388: 24bit display output path

Hi Raj,

You will need to 24bit output in the display controller, not in display pipe driver.

Rgds,

Brijesh

Thanks for the response Brijesh.

Does the display controller driver support 24 bit output in IPNC RDK 3.9.1?

--Narasimha

Hi Brijesh,

We are trying to display through HDMI.

This is my Display controller config
{VPS_DC_BP0_INPUT_PATH, VPS_DC_VCOMP_MUX},
{VPS_DC_VCOMP_MUX, VPS_DC_VCOMP},
{VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND},

{VPS_DC_BP1_INPUT_PATH, VPS_DC_HDCOMP_MUX} ,
{VPS_DC_HDCOMP_MUX, VPS_DC_CIG_PIP_INPUT} ,
{VPS_DC_CIG_PIP_OUTPUT, VPS_DC_DVO2_BLEND},

{VPS_DC_MAIN_INPUT_PATH, VPS_DC_VCOMP},
{VPS_DC_AUX_INPUT_PATH, VPS_DC_HDCOMP_MUX}

This is my display id
displayId = DISPLAY_LINK_DISPLAY_SC1

Wil it support 24 bit output in the display controller path?

Are they tested 24 bit output in the display controller in IPNC RDK 3.9.1?

Regards,
RAJM

Raj,

There should be some ioctl like SET_VENC_OUTPUT. Here you need to set the 24bit output mode.

Regards,
Brijesh

Hi Brijesh,

I have changed

pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dataFormat = SYSTEM_DF_RGB24_888;

In System_displayCtrlInit function we set the

/* Set output in display controller */
if (pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].enable) {
Vps_rprintf("IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_DVO2\n");
retVal = FVID2_control(
gSystem_objVpss.fvidDisplayCtrl,
IOCTL_VPS_DCTRL_SET_VENC_OUTPUT,
&pPrm->deviceParams[SYSTEM_DC_VENC_DVO2].outputInfo,
NULL);
UTILS_assert(retVal == FVID2_SOK);
}

Display link create failed

4580: Assertion @ Line: 848 in links_m3vpss/display/displayLink_drv.c: status == FVID2_SOK : failed !!!

line number 848 is

/* For the DEI Display instances, set the DEI params */
if (DisplayLink_drvIsDeiDisplayDrv(pObj))
{
status = DisplayLink_drvSetDeiDispPrms(pObj, pFormat);
}
else
{
status = FVID2_setFormat(pObj->displayHndl, pFormat);
}

848 - ------> UTILS_assert(status == FVID2_SOK);



Regards,
RAJM

Hi Raj,

Ths failure has nothing to do with the 24bit output mode. It means that you are trying to set some wrong format information. it is not dependent on 24bit output, you should get this error even if you have 16bit or 8bit output..

Rgds,
Brijes

Hi Brijesh,

Ths failure has nothing to do with the 24bit output mode. 

Yes.

It means that you are trying to set some wrong format information. 

I got error only when i set FVID2_DF_RGB24_888.

I set below param

  pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoFmt = VDIS_DVOFMT_TRIPLECHAN_DISCSYNC;//RAJM VDIS_DVOFMT_DOUBLECHAN;
  pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dataFormat = SYSTEM_DF_RGB24_888;

Then set through IOCTL below is my log

[m3vpss ] RAJM outputInfo.dataFormat = 4103

[m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_DVO2

[m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_HDMI

[m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_SD

[m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_OUTPUT SYSTEM_DC_VENC_HDCOMP

[m3vpss ] IOCTL_VPS_DCTRL_SET_VENC_CLK_SRC ###################

[m3vpss ] HDCOMPCLK

[m3vpss ]  4027: CAPTURE: Create in progress !!!

[m3vpss ]  4064: CAPTURE: VIP0 PortA capture mode is [24-bit, Non-mux Discrete Sync - ACTVID_VSYNC] !!!

[m3vpss ] CAPTURE::HEAPID:0    USED:192

[m3vpss ]  4564: CAPTURE: Create Done !!!

[m3vpss ]  4565: DISPLAY: Create in progress !!!

[m3vpss ] DisplayId = 3,DataFormat = 4103

[m3vpss ] DataFormat = 4103

[m3vpss ] BP1 displayInstId = 1

[m3vpss ]  4567: Assertion @ Line: 848 in links_m3vpss/display/displayLink_drv.c: status == FVID2_SOK : failed !!!

Regards,

RAJM

Are you trying to set the same format in the display pipeline also?
DisplayId = 3,DataFormat = 4103

Please note that display video pipelines do not support RGB24bit format. Use only YUV formats on the display pipelines.

Regards,
Brijesh

Hi Brijesh,

Are you trying to set the same format in the display pipeline also?
DisplayId = 3,DataFormat = 4103

yes.

ok, we understand that display driver support rgb 24bit format  but display link doesnot support rgb 24bit support.

we know 16bit support. is yuv 24bit support?

is there any specific reason for not support rgb 24bit in display video pipeline?

if we want to support 24bit rgb in display video pipline what changes we need to do?

Regards,

RAJM

Hi Brijesh,

I can able to get RGB 24bit output mode on VOUT1 port(DVO2).

Below is my settings:

I use IOCTL_VPS_DCTRL_SET_VENC_OUTPUT to set the 24bit output mode(RGB24_888) on display controller.

I use YUV format(SYSTEM_DF_YUV420SP_UV) on display video pipelines.

So basically Display controller convert YUV to RGB?

Regards,
RAJ M

Hi Brijesh.

Thanks for the clarification

One more doubts

Have TI tested HDCOMP output on DM388?

Regards,
RAJ M

Yes, but only component output. PS HDCOMP is always tied with one of the other HD VENC as it does not have independent clock..

Regards,
Brijesh