AM3703: SDRC burst read

The cortex-A8 has a cache line size of 64 bytes, so any read from cacheable memory that doesn't hit in cache will result in a 64-byte linefill, performed as a four quadword (16-byte) or eight doubleword (8-byte) read burst, depending on whether the AXI interface of the cortex-a8 has been configured to be 128- or 64-bit (I wasn't able to quickly find this for the am37xx). The linefill is a wrap-mode burst with the "critical" quadword/doubleword (i.e. the one containing the first byte of the original read) first. Subsequent reads from anywhere in the same 64-byte cache line will hit in cache and not result in any request to SDRC.

SDRC will translate the read burst of the cortex-a8 into a sequence of read bursts on the RAM interface. The burst length on the RAM interface depends on the configuration:

• SDR, 16-bit width: 4 bytes
• SDR, 32-bit width: 8 bytes
• DDR, 16-bit width: 8 bytes
• DDR, 32-bit width: 16 bytes

This is mostly straighforward, with one exception: if the cortex-a8 has a 64-bit interface, the RAM burst length is 16 bytes (32-bit DDR), and bit 3 is set in the original request address, then the read burst from the cortex-a8 is not aligned to the RAM burst length. This isn't much of a problem however, since read bursts can be interrupted by other reads (and likewise write bursts by writes) when half the burst has been transferred. For example, reading from 0x8000001C would trigger a linefill of 0x80000000-0x8000003F starting at 0x80000018 and ultimately the following sequence of words would be transferred from RAM:

0x80000018 0x8000001C (burst interrupted, would otherwise transfer 0x80000010 0x80000014)
0x80000020 0x80000024 0x80000028 0x8000002C
0x80000030 0x80000034 0x80000038 0x8000003C
0x80000000 0x80000004 0x80000008 0x8000000C
0x80000010 0x80000014 (burst may be interrupted by another read, otherwise 0x80000018 0x8000001C)

When performing a non-cacheable read, SDRC still has to transfer half a RAM burst at minimum before it can do another read, so this may result in inefficient use of memory bandwidth.  For example, in the same situation as above, a non-cacheable read would result in:

0x8000001C 0x80000010 (burst may be interrupted by another read, otherwise 0x80000014 0x80000018)

The superfluous data transferred from RAM is discarded.