• State Resolved
  • Locked Locked
  • Replies 15 replies
  • Answers 7 answers
  • Subscribers 98 subscribers
  • Views 3222 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TCI6630K2L: DFE Configuration for non-LTE application

Kenneth Witham
Intellectual 350 points
Part Number: TCI6630K2L
Other Parts Discussed in Thread: RFSDK, , 66AK2L06

Hello,

So I am currently working on implementing the K2L chip in a system with a DAC over the JESD204B interface. I am currently working on using the DFE LLD included in the PDK to program and test the dfe basing my design off of the dfe and iqnet2 examples included with the PDK. These examples include a set of pre-configured DFE register values. I am assuming these are the same that the RFSDK stores in its tgtcfg files as the register addresses are mostly the same. I need to configure our DFE to accept 2 JESD RX pairs and 2 JESD TX pairs.

My problem is that the RFSDK includes configurations and target register configurations for only LTE and WCDMA applications. If I am doing our design for a custom signal size which target register configuration should I use for the DFE? Also where are the DFE configuration registers documented and if not why not?

Thanks so much!

  • 0
    TI__Mastermind 37500 points

    Hello,

    In the TCI6630K2L or 66aK2L06 devices.

    There are not DFE adjustable registers, there are TGTCFG DFE precompiled examples, with IQN baseband, and Serdes compatible configurations.  The DFE cmd tool is an internal tool, that describes the 18 subblocks within DFE.   There are 2 third party developers, Azcom (Italy), and Comm Agility (England) external from TI that have access to the registers.  The reason why is that some interfaces need to have multi-section simulation to validate new configurations.   

    The DFE can be configured for 2 or 4 JESD lanes of Tx and Rx.  Within the DFE, the data rate transferred for Tx and Rx are normally the same complex rate.  The ADC side, does support real single rate HD=0.

    On the Baseband side, we have to setup each IQN channel, as complex data.   Beyond LTE we have tested 46.08, 61,44, 92.16, 122.88Msps.

    WCDMA, LTE - 3.84, 7.68,15.36, 30.72e6

    The clock subsystem with SYSREF, supports a DFE clock of 245.76, or 368.64, there is some clock gating.

    On the Serdes interface, we have tested,  92.16e6,122.88e6, 184.32e6, 245.76e6, 368.64e6 (IQ rate)

    JESD F = 2, 184.32e6 - 3.6864G; 245.76e6 - 4.9152G; 368.64e6 - 7.3728G

    JESD F = 4, 92.16e6 - 3.6864G; 122.88e6 - 4.9152G; 184.32e6 - 7.3728G

    The software for these designs is in the software download.

    There are Adjacent Market designs with illustrated usages of external ADCs and DACs with JESD.   

    is the general TI data area.

     "www.ti.com/.../TIDEP0034"Digital IF, ADC input (complex), DAC output (complex) - parallel IQ L=2,M=2,F=2 - sample rate 245.76e6, JESD rage 4.9152G

    Baseband interface - (2) 61.44Msps complex, assigned to 1 or 2 Transmit, 1 or 2 Receive channels.   

    Digital IF, ADC input (complex), DAC output (complex) - parallel IQ L=2,M=2,F=2 - sample rate 368.64e6, JESD rage 7.3728G

    Baseband interface - (2) 92.16Msps complex, assigned to 1 or 2 Transmit, 1 or 2 Receive channels.

    "www.ti.com/.../TIDEP0060"

    Digital IF, ADC input(real), DAC output (complex) -  parallel IQ L=2,M=2,F=2 - sample rate 245.76e6, JESD rage 4.9152G

    Baseband interface - (1) 122.88Msps complex, assigned to 1 Transmit, 1 Receive channels. 

    "www.ti.com/.../TIDEP0081"

    this is the same IF and baseband DFE, but a diffe

    Digital IF, ADC input (complex), DAC output (complex) - parallel IQ L=2,M=2,F=2 - sample rate 245.76e6, JESD rage 4.9152G

    Baseband interface - (2) 61.44Msps complex, assigned to 1 or 2 Transmit, 1 or 2 Receive channels.   

    Digital IF, ADC input (complex), DAC output (complex) - parallel IQ L=2,M=2,F=2 - sample rate 368.64e6, JESD rage 7.3728G

    Baseband interface - (2) 92.16Msps complex, assigned to 1 or 2 Transmit, 1 or 2 Receive channels.

    Regards,

    Joe Quintal

    Application Engineer

  • 0 in reply to Radio-Joe
    Intellectual 350 points
    So do the registers that are configured in the target configuration file configure all of the parts you listed (JESD settings and Baseband)? Are those the only 2 things I need to worry about configuring correctly with the target configuration file and the rest can be done with the LLD(DDUCs, Summer, JESD rates)?


    Thank you!
  • 0 in reply to Kenneth Witham
    TI__Mastermind 37500 points

    radioselect_usecasefiles.xlsxHello Kenneth,

    The .tgtcfg files, have a specific DFE configuration, the DFE configuration selects the:

    IQN baseband configuration,

    DFE Tx, Rx, Fdbk stream setup,

    JESD and Serdes bit rate.  

    Within the RFSDK constraints, the other items are controlled through RFSDK APIs or custom APIs that are developed.   The RFSDK knows how to program the IQN and Serdes from the radio configuration.    There is a separate compilation of the DFE configuration that matches the above.  There are APIs that change the dynamic register and memory controls of DFE.  

    Yes, the DFE configuration registers, the IQN2 registers / timers, and the Serdes configuation are all done through the Radio Init, and Radio On functions.  The DFE logic section is described in spruhx8a.pdf.

    radioselect_usecasefiles.xlsx - describes what information is contained.  You select the radioselect file, the radioselect file, selects the use case, and other files.

    in the use case file, under "dfeConfig" "configFile" this selects the DFE configuration

    Regards,

    Joe Quintal

  • 0 in reply to Radio-Joe
    Intellectual 350 points
    Hi Joe,

    So I have been able to get our analog front end working with the RFSDK! I have selected a proper tgtcfg and was able to get the JESD up and running and passing data both in and out of the board through that. The problem now is I have to somehow get all of this working from a DSP core outside of Linux. I have been able to successfully get everything working exclusivly running on a DSP core in JESD loopback mode using the loopback tgtcfg file for JESD loopback for the configuration we chose. The only thing I have been unable to get working is the JESD block in the DFE now. I configure everything the same as the RFSDK does I believe but after I have everything started up, when I do the equivalent of "dfecmd JesdStatus", I have valid sync values but both the Tx and Rx sides have "FifoEmpty" errors on the enabled lanes and the sync states and code states are all 0. Is there something I am missing that would cause these errors?

    Thanks so much!
  • 0 in reply to Kenneth Witham
    TI__Mastermind 37500 points
    Hello,
    The key functions are DFE initialization, which relates to the Radio ON. There are several functions that relate to IQN2 startup, Serdes Startup,
    and DFE sectioned startup.

    When you select a JESD loopback, the DFE signal does not leave the DFE module, it loops back the JESD Tx IQ signals to JESD Rx I or IQ signals.

    When you have the Data converter or other JESD connections, the DFE initialization needs to have the serdes initialized. The serdes needs to have the external ADC and DAC initialized before the DFE Initialization. I would check your radio ON functions, and make sure the SPI programming of the data converters is done before your radio on.
    Regards,
    Joe Quintal
  • 0 in reply to Radio-Joe
    Intellectual 350 points

    Hi Joe,

    So I was able to get our Front End working with the DFE! Passing data from the DSP Cores out and seeing it after our DAC. I used the 1x1_2xLTE60_HC_JESD121121x_DEMO1.tgtcfg file with a DFE clock of 368.64 MHz and JESD Rate of 4.9152 GHz. 

    I am just seeing some strange outputs now and am wondering what you think the DFE is doing to my signal. I am feeding the DFE through IQN2 with a 3 MHz sine wave (30.72 samples/period) at the BB sample rate of 92.16 MHz. When I look at the output of my DAC though, it is ouputing a 38MHz sine wave. I have set both the DDUC NCO and TX NCO to frequencies to 0. Is there something else that could be causing this frequency shift? What do I have to change through the DFE LLD in order basically just get a straight signal passthrough the DFE so whatever signal I put in to it comes out at the same frequency at the end?

    Thanks so much!!

    Ken

  • 0 in reply to Kenneth Witham
    TI__Mastermind 37500 points

    Hello Ken

    LTE60 has a baseband sample rate of  92.16Msps.   So a 3Mhz tone at 30.72 will run out of samples at some time.  You would have a 9Mhz tone at 92defbbgel_cap.zip.16Msps and then whatever was in memory.

    There is normally a 1Mhz  or 2Mhz tone built with the examples.  

    Within DFE there is a capture buffer, in the Tx structure, the capture buffer is before and after the DPD section, after the Rx section, and at the feedback portion.   There are also test bus sections.    

    If you are using the 245.76Msps ADC (real) the configuration is using the FS/4 upconversion.   The Resample block after CFR (before DPD) has a mixer that is translating complex to real (since the mixer in the Resample block is not instrumented in the json files, you do not have control of this (ie there are actually 3 mixers (DDUC-Tx, CDFR, and Tx block)  only the first and last one have RFSDK controls.

    Normally the input tone, goes through the DDUC0, and is translated to a lower carrier Ax0, or DDUC1 and is translated to an upper carrier Ax1.

    The DDUC translation is programmed in the DFE register writes, and can then be overwritten by the radio and use case fields.   We try to create two carriers, for some configurations the translation is -32.5, and 32.5, please check the user guide for the plots.  

    So if you have 3Mhz tone at 30.72, you need to regenerate this as 9Mhz for 92.16Msps (LTE60).  You want a 10ms frame.   you can translate the data format and place the BB files in the RFSDK file system.  If you are doing this for Ax1, the DDUC translation of 30Mhz and 9Mhz gives you about 39Mhz.  (the two carriers are combined into one Tx wide stream).  

    At this point I will send some unsupported files, you will need the DFE GEL file, to be able to use the capture buffer to collect files.   You will need to be careful of the end address,  and capture 4K or 8K complex samples using CCS memory capture.  The suggestion is to put 0s for I and Q into one of the carriers, and to put your tone in the other one to verify your frequency translation.  

    I have included in the zip, a method to make you own BB data, a GEL script for capturing various points in DFE, a word document that is an old example (I believe the distortion portion has been fixed).   There are matlab files for converting the saved CCS memory files from the capture buffer.   Given you can look at the BBTx0,1 in -> JESD Tx0 (this is all of Tx), JESD Rx -> Rxout -> BBRx (this is all of Rx).

    This process is likely to generate more questions, but you can work through the word example, and following the DFEGEL file, and matlab you should be able to to track through the processing.

    If you made you own radar select, and use case select, where the DDUC Tx and Rx frequencies are zero, only drive one carrier.  Make the other carrier 0,0 for IQ.

    Sorry for a lot of information,

    Regards,

    Joe Quintal

  • 0 in reply to Radio-Joe
    Intellectual 350 points

    Hi Joe,

    Those files you sent me were super helpful in tracking down the problem! So I set up the DSP to transmit just a DC signal wich gave me a 35MHz signal out of my DAC. This makes me think my signal is 3MHz at BaseBand then a 35MHz signal is getting mixed in somewhere inside the DFE. Using the GEL file you sent me it looks like my signal remains DC up to the CFR output capture. After this, the next capture point is the DPD input which has the 35MHz signal mixed in now. Does this mean that this 35MHz signal is getting mixed in in the CDFR? The documentation does not mention anything about the CDFR doing any mixing so I am a little confused. I verified all the other BB TX signals are 0 as well as the unused CFR so it shouldn't be getting that signal from there. 

    For using the Matlab files you sent me I am using Fs of 92.16 MHz for pre-CDFR signals and 368.64 MHz (DFE clk) for post-CDFR signals. These values give me the values I am expecting and experiencing on the DAC output. (3MHz signal before, 38Mhz signal after) Does this sound right to you?

    Thanks so much! 

    Ken

  • 0 in reply to Kenneth Witham
    TI__Mastermind 37500 points
    Hi Ken,

    BBTx 92.16, Tx DDUC PFIR 1x, Far 2/1x, CIC 1x, Mixer 184.32 Out Tx channel upconverter)
    SumChain 184.32 (combiner) -> CFR 184.32 -> CDFR (resampler stream combiner mixer) 245.76 -> DPD 245.76 -> Tx (stream upconv) 245.76 -> JESDTx 245.76

    The Capture buffer normally is CDFR (DPDin), and DPD out, there are extensions to BBTx, JESD Tx

    JESD Rx (can be real or complex) -> Rx (stream downconvert) Dec2 (typically Rxingated clk / (2*numRx streams)) -(A)
    (A)- DDUC (Rx stream select) -> Rxchan Mixer -> CIC x1 -> Farrow 1x -> PFIR 1x -> BBRx

    JESD Rx (must be complex) -> Feedback -> capture buffer

    The Capture buffer normally is Feedback, or Rx Imb output (effectively Rx out), there are extensions to BBRx and JESD Rx

    In your application, we discussed the CDFR stream combiner resamples and mixes each Tx stream. If you want to control the mixing from the RFSDK, then the mixing in Tx DDUC will have less Tx frequency translation.

    RFSDK controls Tx DDUC Mixer (channel mixer), Tx Block Stream Mixer, (CDFR Tx stream Mixer is not controlled)
    Rx block - stream mixer, Rx DDUC Mixer (channel mixer)
    Feedback block - stream mixer

    (ie you would have to zero specific words in the DFE configuration file, then you would modify the radio select, use case select.

    Regards,
    Joe Quintal
  • 0 in reply to Radio-Joe
    Intellectual 350 points

    Hi Joe,

    I have set the following to zero in the radio settings file:

    cfr.postgain, cfr.pregain, summerGain, txNco, baseband.nco

    After doing this, I am still seeing the 35MHz signal out of my DAC with a DC signal on AxC0 and a zero signal on AxC1. Is there anything else I can change to remove this carrier signal? What else could be adding this in the signal chain?

    Thanks so much,

    Ken

  • 0 in reply to Kenneth Witham
    TI__Mastermind 37500 points
    Hello,
    That is because the CDFR Mixers are not set by RFSDK. If you want the CDFR mixers to be zero, and you want to control the 2 carriers with the DDUC0 Ch0 (Axc0) and DDUC1 Ch0 (Axc1), I need the exact name of the DFE configuration you are using.

    The CDFR mixers are used to get as wide a tuning range as possible. The carriers are offset from 0IF at the 245.76 or 368.64Msps rate. The rate for the 2 car / DDUC can be 92.16Msps, the 1 car/DDUC can be 184.32Msps.

    I will look and see what I can suggest, once you have sent the exact DFE configuration file you are using.
    Regards,
    Joe Quintal
  • 0 in reply to Radio-Joe
    Intellectual 350 points

    Hi Joe,

    I have attached the use case, radio configuration, and target config files I have been using below. I am using the 1x1-2xLTE60-HC-JESD121121x-DEMO1 radio configuration that shipped with RFSDK 2.0.7 .  The only modification I have done to that is changing the BB and TX NCO value in the radio config file to 0. 

    My plan is to have 3 AxCs that will all map to the same antenna but if that is not possible I will be able to use only 1 since only one AxC is going to be transmitting at a time. I would like to transmit square wave data out of our Keystone device that has no carrier signal since our carrier signal will be added later in the signal chain with external hardware.

    Thanks for all your help,

    Ken

    /cfs-file/__key/communityserver-discussions-components-files/791/5023.modified_5F00_1x1_2D00_2xLTE60_2D00_HC_2D00_JESD121121x_2D00_DEMO1.zip

  • 0 in reply to Kenneth Witham
    TI__Mastermind 37500 points

    Hello Ken,

    The DFE target configuration files, are in the hex address (relative to DFE), hex data format.

    The different blocks in DFE, have relative offsets from the 0x24000000 base address for the SOC.   The programming file

    does not include this base address.

    The CDFR block starts at offset, 

    cdfr0 0x1000000 

    The registers and memories within DFE can be accesses mostly as 32bit values.   

    In the register offsets, there are 4 Mixer frequency, phase offset sections.   If you want to manage the carrier offset using the 

    DDUC0-Tx car0 (Axc0), and DDUC1-Tx car0 (Axc1).  You can try to copy the DFE configuration file to a new name, x1000018 to x10000034 values

    should be set to 0.   

    01000018 C71C71C7
    0100001C 0000E7B1
    01000020 00000000
    01000024 00000000
    01000028 38E38E39
    0100002C 0000184E
    01000030 00000000
    01000034 00000000

    The frequency word is a 48bit value signed integer (bits 47-16), (bits 15-0, phase bits 15-0)

    The tuning frequency is based on (signed int)/2^47*Mixer sample rate.

    The CDFR mode of operation applies the two Tx streams at DFE clock/2 to the two resamplers, then to the two mixers, then the summer.

    Ideally setting this to 0 should provide 0mix.   Then you have to use the Baseband NCO (DDUC Tx NCO) for control.

    REgards,

    Joe Quintal

      

    Remember to modify the 

     

  • 0 in reply to Radio-Joe
    Intellectual 350 points

    Thank you so much! That worked perfectly! Getting nice straight data through with no modification now.

    I am finishing up the processing chain now using the GEL file you sent me for capturing data throughout the DFE. I am currently seeing the data I want all the way through to DFE BB_RX0. My data shows up how I want it when capturing at the test point on RX0 in BaseBand but after that the data does not appear to make it to PKTDMA because all the packets that the DSP are recieving are empty. It appears like the timers are operating properly since data is flowing out of the DFE properly and packets are streaming out of IQN2, but the rx packets look like my data when I capture a blank signal in the DFE (values between -50 and -100 (noise)). How does the connection between the DFE and IQN2 AID work? I must be setting up something wrong in IQN2. My set up: (2 LTE60 AxC, 8 CtlChannels, CPType none, packet size 4608, sample rate 92160) .

    Thanks so much!

    Ken

  • 0 in reply to Kenneth Witham
    TI__Mastermind 37500 points

    Hello,

    I would go back to the closest existing RFSDK file set, and trace through the code until IQN2 is programmed, and save off the values.  This is in C code, so I would imagine you could put them in an array.

    There are EE registers in IQN that provide error events.  Unfortunately I am not an IQN2 support person.  I will ask him, and try to get feedback.

    Regards,

    Joe Quintal