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Linux/AM5716: UDHCPC not working on MII1

Part Number: AM5716

Tool/software: Linux

Hi,

We are using AM5716 processor's MII1 port and is interfaced with KSZ8091MLX PHY. We have connected the MDI side to DHCP network and see that link is up on ifconfig eth1 up command. However, it doesn't get the ip address after udhcpc -i eth1 command. We have verified the pin-mux settings and hardware connections and is fine.

Can you please point us to a document or reference design where MII interface is used and what all settings are required to be done in AM5716 to support MII1 interface apart from Pin-Mux?

Please note that we have also used RGMII0 port and this works fine with the same setup.

Regards

Raja

  • Please follow this checklist and post results here: processors.wiki.ti.com/.../5x_CPSW
  • Hi Raja,

    The checklist that Biser posted will ask you to post results of ethtool that indicate that a link is detected and look at statistics to see if there are any HW errors along with other steps to make sure that packets are at least leaving eth1.

    One additional question since it looks like the link is reporting up, you must have two unique subnets, one subnet to plug into eth0 and a different one for eth1. If you don't have two unique subnets, disconnect eth0 and leave eth1 plugged in and check if it gets it an ip address.

    Best Regards,
    Schuyler
  • Thanks Biser for the checklist. We are going through the same and will share the log shortly.

    Dear Schuyler,

    Yes, we don't have two unique subnets and hence we have set ifconfig eth0 down before setting eth1 up.

    Meanwhile, we have done some more experiments and below are the observations.

    1. By default, Auto-negotiation is enabled in PHY and it gets set to 100Mbps. However, ip address is not allocated.

    2. When we force it to 10Mbps using ethtool command, it is able to get ip address and ping test also passes.

    3. When we force it to 100Mbps using ethtool command, it is not able to get ip address.

    We doubt it to be a layout related timing issue, as we have length matched the TX (TXCLK, TXD0-3, TXEN and TXER) and RX (RXCLK, RXD0-3, RXER, RXDV, COL and CRS) groups each within 200 mils. Is there any processor related delay we need to provide similar to that mentioned for RGMII0 and RGMII1 interface?

    Regards

    Raja

  • Hi,

    Just to update. We were writing wrong value in one of the PHY Register 0x1F (Disable Scrambler). Now with the default values, it is working fine for 100Mbps. Thanks for the support.

    Regards
    Raja