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AECLKIN frequency on DM643

KatieRoberts-Hoffman
Intellectual 2235 points

Is it possible to use 133MHz AECLKIN with DM643-500? According to the table 5-17 on p.84 minimum cycle time of 6 ns seems to apply to both 500MHz and 600MHz devices. It notes that 100MHz AECLKIN is achievable at CPU 500MHz and 133MHz ECLKIN at 600MHz. As opposed, for example, to CLKIN requirements (tables 5-13, 5-14), where -500 and -600 specs differ and are clearly separated.

  • 0
    TI__Expert 8260 points

    The note tells to meet the requirements metioned in section 5.8.1 EMIF Device Specific Information (on page 86). If you meet those requirements, then you can have 100-MHz EMIF operation on 500MHz device and 133-MHz operation on 600-MHz device. In this case, you no need to do any timing analysis.

    If you don't meet the requiments of the section 5.8.1 or you want to run AEMIF at your own speed, then timing analysis must be done to verify all AC timings are met. Following is a copy and paste from section 5.8.1 of the DM643 data sheet:

    "Other configurations may be possible, but timing analysis must be done to verify all AC timings are met. Verification of AC timings is mandatory when using configurations other than those specified above. TI recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings."

    Regards, Srirami.

  • 0 in reply to srirami
    Expert 1055 points

    Srirami,

    it's still looks ambiguous. Suppose the the EMIF requirements from p.86 are met. Then, according to table 5-17 the AECLKIN cycle time for the 500MHz device is 6 ns, which corresponds to 133 MHz clock. Note 4 only says that "on the 500MHz devices, the 100MHz operation is achievable", it doesn't say that 100MHz is the maximum clock (which would then contradict Table 5-17).

    Could you please confirm the minimum AECLKIN cycle time for the 500MHz device (provided the requirements from p.86 are met)?  Is it 6ns as the data sheet claims or 10ns?

  • 0 in reply to Alexander Khvilivitzky
    TI__Expert 8260 points

    Alexander,

    The 6ns corresponds to 166.6MHz, not 133MHz. The 6ns cycle time applies to both 500MHz and 600MHz devices. This timing is based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements.

    Coming to your question, yes 133MHz AEMIF on 500MHz device may be possible, but timing analysis must be done to verify all AC timings are met. Verification of AC timings is mandatory.

    Section 5.8.1 tells about one configuration that TI verified.

    Note that, EMIFA clock can be an internal or external clock, which is selectable by AEA[20:19] pins. If it's an internal clock, the EMIFA clock can be CPU/4 (125MHz) or CPU/6 (83.3MHz). You have to chose external clock to run at 133MHz.

    Regards, Srirami.

     

  • 0 in reply to srirami
    Expert 1055 points

    Got it. Thanks, Srirami!