AM3351: DDR3 software leveling without CCS

Dirk

Is there an option to populate a JTAG interface on any of the proto boards? We could derive the optimal values from one board and use this on subsequent boards. Can you share more details on the customer board layout, implementation etc. so I can provide better guidance on how to deal with this situation.

Regards, Siva

There came up some additional questions:

1)

If TIs way to calibrate DD3 is understood correct, tool is assuming, that length of traces for netgroups DQS0 and DQS1 are of approx of same length.

In description DS chap 7.7.2.3.6.2 explicitely is mentioned, that length matching is applicable for a byte.

Is it correct, that so 2 sets of calibration values should be existing ?

This is not to be find in TI tools.

How is foot note of chapter 7.7.2.3.6.1 to be interpreted ?

Does it mean, that a DDR3  interface routed with trace length of 300mil can be used on same layout with DDR2 ?
Or if only DDR3 is used, 300mil are not needed ?

2)

Question regarding of data representation on copy of data:

Assuming R0 rehister (32b big endian) has to be copied into DDR memory. But DDR mem is little-endian organised.How is copy sequence and final order in DDR memory ?

Here customers approach to explain.

DJ-NG said:

There came up some additional questions:

1)

If TIs way to calibrate DD3 is understood correct, tool is assuming, that length of traces for netgroups DQS0 and DQS1 are of approx of same length.

In description DS chap 7.7.2.3.6.2 explicitely is mentioned, that length matching is applicable for a byte.

Is it correct, that so 2 sets of calibration values should be existing ?

This is not to be find in TI tools.

For the DDR SW leveling,  the tool basically averages the DQS across the 2 bytes. We have found that for the x16 DDR interface on AM335x and utilizing our board routing guidelines, this methodology provides acceptable performance to meet the DRAM timings with the interface running at 400MHz clock rate.

DJ-NG said:

How is foot note of chapter 7.7.2.3.6.1 to be interpreted ?

Does it mean, that a DDR3  interface routed with trace length of 300mil can be used on same layout with DDR2 ?
Or if only DDR3 is used, 300mil are not needed ?

Foot note is basically describing the longest Manhattan length for the address control bus. There is an additional 300 mil on top of CACLMY to help route the address bus below the DDR3 part to the BGA as shown in the Figure. The 300 mils is not related to re-using the layout for DDR2. Please let us know if this is still not clear.

DJ-NG said:

2)

Question regarding of data representation on copy of data:

Assuming R0 rehister (32b big endian) has to be copied into DDR memory. But DDR mem is little-endian organised.How is copy sequence and final order in DDR memory ?

Here customers approach to explain.