RTOS/AM4378: PRU1 sometimes fails to read data from PRU0

Mare,

Have you tried to add some delay in your while loop to isolate the problem? I think there is chance that the bus is blocked due to the continuous access from PRU0.

Regards,
Garrett

Hi Garrett!

I made some "nop" lines in while. It is difficult to confirm solution, because error was pretty random.
Please can you explain next:

1.) in .cfg file:

var peripheralAttrs = {
    type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
    tex: 1,
    bufferable : false,                // bufferable - true
    cacheable  : false,                // cacheable
    shareable  : true,                // shareable
    noexecute  : false,                 // not executable
};

I put bufferable to false. if Bufferable=true mean that when ARM write on PRU location...data are not immediately written. Right?
So in my case bufferable=false is OK?.. because when I need to send something to PRU I also use interrupt for signaling to PRU that data are ready for reading?

2.) I just found case when PRU write some data in "shared data" in his local RAM (PRU0 DATA RAM) and make interrupt to ARM. ARM read data and data are corrupt! First structure (uint32_t) member is correct other structure members are in previews state. For reading and writing with ARM to PRU0 RAM  I use HW_RD_REG32_RAW and HW_WR_REG32_RAW function. What is going on? Has PRU also some delay/buffering to his RAM?

p.s. I am very grateful for your help!

Regards,
Mare

Mare,

1) "The Bufferable (B), Cacheable (C), and Type Extension (TEX) bit names are inherited from earlier versions of the
architecture. These names no longer adequately describe the function of the B, C, and TEX bits." You may look into the ARM® Architecture Reference Manual for the details of the memory region attributes. But yes, set bufferable=false is OK and with cacheable=false, the memory is defined as strongly-ordered.

2) Do you have MEM_BARRIER_DISABLE defined in your project? These HW_RD_REG32_RAW and HW_WR_REG32_RAW functions from hw_types.h has a barrier asm("dsb") that can be disabled if you have MEM_BARRIER_DISABLE defined in your project.

Regards,
Garrett

Garrett,

Thanks for "1.)".

About "2.)":

I check function:

static inline void HW_MEM_BARRIER(void)
{
#if (defined(__ARMv7) || defined(__TI_ARM_V7__))
#ifndef MEM_BARRIER_DISABLE
    asm("    dsb");
#endif
#endif
}

MEM_BARRIER_DISABLE is not defined!
Also __ARMv7 or __TI_ARM_V7__ are missing. They should be defined...right?
Now DSB instruction is disabled.
This is by default in pdk_am437x_1_0_6 right?

Regards, Mare