Part Number: TMS320C6678
Other Parts Discussed in Thread: SYSBIOS
Tool/software: TI-RTOS
Dear TI,
We are using C6678 processor and SYSBIOS OS for our project. Can some one please help me in enabling the L2 cache, I have referred the corepac and cache user guide from TI, but nothing helped us. I have done the below changes to enable the cache in .cfg and platform.xdc files in our project.
From *.cfg file:
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var ti_sysbios_family_c66_Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
ti_sysbios_family_c66_Cache.setMarMeta(0x80000000, 0x0010000, ti_sysbios_family_c66_Cache.PC | ti_sysbios_family_c66_Cache.PCX | ti_sysbios_family_c66_Cache.PFX | ti_sysbios_family_c66_Cache.WTE);
From paltform.xdc
==============
l1DMode: "32k",
l1PMode: "32k",
l2Mode: "64k",
After compiling the project, if I go and see the memory map file if the particular memory range is cache enabled, then either code or data should not place , but I am seeing some text code is placing over there. That means cache is not enabled for the particular memory. Can some one please help me?
L2SRAM_START_CACHE 00800000 00010000 00001aa0 0000e560 RW X
Thanks,
-Pavan
