reading data from NOR flash memory and writting on DDR

Marcio said:

When I put the Modules on L2 CACHE and run in NOR, it works.
But, when I put the Modules on DDR2 and run again, it doesn,t work.

It sounds like you are already able to get your code/data into the NOR, so it seems you are just unable to utilize DDR2? If you open a view memory window to the DDR2 space (0x80000000) can you edit values successfully?

Yes, I can edit values on DDR2 space.

Let me explain better.

I did a program where I do a toggle in one GPIO.
Following the sequence of configuration:

MainInit(){
PLL
PINMUX
VDD3P3V
GPIO
}

In the ".gel" file I configurated the MEMORY MAP and DDR2's clock on StartUp()

In the ".cmd" file I configurated the SECTIONS like this:
SECTIONS
{
 .text  > DDR2
 .stack > CACHE_L2
    .
    .
    .
}

So when I put all the sections in CACHE_L2 and use FlashBurn
 to burn the program in the NOR, it works. In the Debuger time it also works.
But, when I put all the sections in DDR2 and use FlashBurn
 to burn the program in the NOR,it doesn't work. In the debuger time it works.

My question is, what I need to do, or what the sequence I need to do,
to my program works into DDR2 after boot?

I have some questions about the boot sequence on DM6437.

EVM is configured as:

FASTBOOT = 1
AEM[2:0] = 001b
BOOTMODE[3:0] = 0100b

Using SPRAAG0 doc sequence:
"... EMIF FASTBOOT sequence:
1. Programs the PLL using the PLL multiplier selected by the value of the AEM and PLLMS[2:0] pins as shown in Table 6.
2. Reads the value of the 8_16 pin as latched into the BOOTCFG register and sets the EMIF data width accordingly.
3. Fetches the AIS data from the external memory and processes the AIS commands until the JUMP_CLOSE command is encountered.
4. Branches to the application start address given in the JUMP CLOSE command. "


So I think the program will start at address 0x0010 0000 and sets the PLL and EMIF automatically. 
After this, it starts to copy the sections to the space for each other was configurated.
Finishing it, starts the program at point _c_init().

If I configure the SECTIONS in the CACHE_L2, I think that the process will allocate the data in the CACHE_L2.

If I configure the SECTIONS in the DDR2 I think that the process will allocate the data in the DRR2.

But, for now, I need to configure the DDR2 before the process allocate the data in the DDR2.
So, my questions are: 
1) On the program, Where I have to configure DDR2 access, before it starts to allocate the data? 
2) Does the sequence above correct or I did something wrong?